Hi,
sorry for my long time of inactivity doe to other jobs. A while ago I
send a patch making arm_adi_v5.c independent from transport layer. I
created a third solution:
To preserve the performance I changed the interface to the transport
layer. Both, dap_queue_ap_write and dap_queue_ap_read gets a pointer to
a data array not a single value. The adi_v5_jtag now implements the loop
reading the registers via jtag transport layer. So other transports like
SWD can implement it's own efficient method reading a register multiple
times.
I don't know if the patch works, but it should be easy to adapt.
Best regards,
Svenwhile
Am 13.03.2012 05:30, schrieb simonqian.openocd:
> Hi,
> Attachment is the patch for the latest OpenOCD.
> Versaloon forum has been moved to
> http://groups.yahoo.com/group/versaloon/.
> Actually, there are many patches to implement SWD.
> I just want to find a start point, and original JTAG code is least
> affected.
> So I want first make OpenOCD transport independent, so that JTAG is
> also usable(and testable) and meanwhile SWD code can be commited.
> ------------------------------------------------------------------------
> simonqian.openocd
> *From:* Peter Stuge <mailto:pe...@stuge.se>
> *Date:* 2012-03-13 11:53
> *To:* openocd-devel <mailto:openocd-devel@lists.sourceforge.net>
> *Subject:* Re: [OpenOCD-devel] make arm_adi_v5.c transport independent
> Hi Simon,
> simonqian.openocd wrote:
> > I have recently read libswd code
> Thank you very much for looking into this!
> > and want to somewhat push the SWD progress.
> > First modification should be to arm_adi_v5.c and/or adi_v5_jtag/swd.c,
> > so that arm_adi_v5.c could be transport independent.
> >
> > I found both libswd and my SWD patch modify 2 main functions in
> > arm_adi_v5.c, which are ahbap_debugport_init and mem_ap_read_buf_u32.
> Where can your most recent SWD patch be found?
> http://www.versaloon.com/doc/versaloon/doc_versaloon_openocd_urjtag.html
> has a patch from 2010-11-04, and unfortunately the versaloon.com
> Forum seems to be unavailable since some time.
> > ahbap_debugport_init should obviously be modified to initialize SWD
> > if SWD transport is sellected.
> > And mem_ap_read_buf_u32 should not call adi_jtag_dp_scan, or
> > implement mem_ap_read_buf_u32_jtag and mem_ap_read_buf_u32_swd.
> >
> > 2 solutions:
> > 1. In my SWD patch, I add queue_dp_scan to dap->op, and implement
> > dap_queue_dp_scan to call dap->op->queue_dp_scan instead of JTAG ones.
> > And queue_dp_scan is implemented in both jtag_dp_ops and swd_dp_ops.
> > 2. In libswd code, 2 functions are implemented for mem_ap_read_buf_u32,
> > which are mem_ap_read_buf_u32_jtag and mem_ap_read_buf_u32_swd.
> > And they are called in mem_ap_read_buf_u32 according to the transport
> > sellected.
> >
> > So the result is simple, choose one of the 2 methods above.
> I can't make a useful comment at this point, but I would like to look
> at the code and make a suggestion.
> > Both are OK for me if we can make progress.
> > And I can prepare the patch if any one want to try.
> Thank you for this effort. I will be very happy to test patches.
> //Peter
> ------------------------------------------------------------------------------
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diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 75461c3..498cab0 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -86,7 +86,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
struct arm_jtag *jtag_info = dap->jtag_info;
struct scan_field fields[2];
uint8_t out_addr_buf;
- int retval;
+ int retval = ERROR_OK;
retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
@@ -153,41 +153,48 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
return retval;
}
-/**
- * Utility to write AP registers.
- */
-static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
- uint8_t reg_addr, uint8_t *outvalue)
-{
- return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
- outvalue, NULL, NULL);
-}
-
static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
- uint32_t outvalue, uint32_t *invalue)
+ uint32_t *buffer, uint32_t count)
{
- int retval;
+ int retval = ERROR_OK;
- /* Issue the read or write */
- retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
- RnW, outvalue, NULL, NULL);
- if (retval != ERROR_OK)
- return retval;
+ if (RnW == DPAP_READ) {
+ retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
+ DPAP_READ, 0, NULL, NULL);
+ if (retval != ERROR_OK)
+ return retval;
+ while(count > 1){
+ retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
+ DPAP_READ, 0, buffer, &dap->ack);
+ if (retval != ERROR_OK)
+ return retval;
+ buffer++;
+ count--;
+ }
+ retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC, DP_RDBUFF,
+ DPAP_READ, 0, buffer, &dap->ack);
+ if (retval != ERROR_OK)
+ return retval;
+ }else{
+ assert(buffer != NULL);
+ while(count > 0){
+ retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
+ RnW, *buffer, NULL, NULL);
+ if (retval != ERROR_OK)
+ return retval;
+ buffer++;
+ count--;
+ }
+ }
- /* For reads, collect posted value; RDBUFF has no other effect.
- * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
- */
- if ((RnW == DPAP_READ) && (invalue != NULL))
- retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
- DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
return retval;
}
static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
{
int retval;
- uint32_t ctrlstat;
+ uint32_t ctrlstat, tmp;
/* too expensive to call keep_alive() here */
@@ -220,7 +227,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
* but collect its ACK status.
*/
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, &ctrlstat, 1);
if (retval != ERROR_OK)
return retval;
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -257,7 +264,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
}
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, &ctrlstat, 1);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
@@ -304,14 +311,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
LOG_ERROR("JTAG-DP STICKY ERROR");
/* Clear Sticky Error Bits */
+ tmp = dap->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR;
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_WRITE,
- dap->dp_ctrl_stat | SSTICKYORUN
- | SSTICKYERR, NULL);
+ &tmp, 1);
if (retval != ERROR_OK)
return retval;
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, &ctrlstat, 1);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
@@ -320,12 +327,12 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
retval = dap_queue_ap_read(dap,
- AP_REG_CSW, &mem_ap_csw);
+ AP_REG_CSW, &mem_ap_csw, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(dap,
- AP_REG_TAR, &mem_ap_tar);
+ AP_REG_TAR, &mem_ap_tar, 1);
if (retval != ERROR_OK)
return retval;
@@ -373,14 +380,14 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- reg, DPAP_READ, 0, data);
+ reg, DPAP_READ, data, 1);
}
static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- reg, DPAP_WRITE, data, NULL);
+ reg, DPAP_WRITE, &data, 1);
}
/** Select the AP register bank matching bits 7:4 of reg. */
@@ -398,7 +405,7 @@ static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
}
static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
- uint32_t *data)
+ uint32_t *data, uint32_t count)
{
int retval = jtag_ap_q_bankselect(dap, reg);
@@ -406,21 +413,18 @@ static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
return retval;
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
- DPAP_READ, 0, data);
+ DPAP_READ, data, count);
}
static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
- uint32_t data)
+ uint32_t *data, uint32_t count)
{
- uint8_t out_value_buf[4];
-
int retval = jtag_ap_q_bankselect(dap, reg);
if (retval != ERROR_OK)
return retval;
- buf_set_u32(out_value_buf, 0, 32, data);
-
- return adi_jtag_ap_write_check(dap, reg, out_value_buf);
+ return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
+ DPAP_WRITE, data, count);
}
static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 5a3570d..084dcca 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -84,19 +84,35 @@ static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
- uint32_t *data)
+ uint32_t *data, uint32_t size)
{
+ int retval = ERROR_OK;
// REVISIT APSEL ...
// REVISIT status return ...
- return swd->read_reg(swd_cmd(true, true, reg), data);
+ while (size > 0){
+ retval = swd->read_reg(swd_cmd(false, true, reg), data);
+ if (retval != ERROR_OK)
+ return retval;
+ data += 1;
+ size--;
+ }
+ return retval;
}
static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
- uint32_t data)
+ uint32_t *data, uint32_t size)
{
+ int retval = ERROR_OK;
// REVISIT APSEL ...
// REVISIT status return ...
- return swd->write_reg(swd_cmd(false, true, reg), data);
+ while (size > 0){
+ retval = swd->write_reg(swd_cmd(false, true, reg), *data);
+ if (retval != ERROR_OK)
+ return retval;
+ data += 1;
+ size--;
+ }
+ return retval;
}
static int (swd_queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack)
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index f8a2e22..4a3d671 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -143,7 +143,7 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
if (csw != dap->ap_csw_value)
{
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
- retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
+ retval = dap_queue_ap_write(dap, AP_REG_CSW, &csw, 1);
if (retval != ERROR_OK)
return retval;
dap->ap_csw_value = csw;
@@ -151,7 +151,7 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
if (tar != dap->ap_tar_value)
{
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
+ retval = dap_queue_ap_write(dap, AP_REG_TAR, &tar, 1);
if (retval != ERROR_OK)
return retval;
dap->ap_tar_value = tar;
@@ -186,7 +186,7 @@ int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
+ return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value, 1);
}
/**
@@ -238,7 +238,7 @@ int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
return retval;
return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
- value);
+ &value, 1);
}
/**
@@ -313,13 +313,9 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count
if (retval != ERROR_OK)
return retval;
- for (writecount = 0; writecount < blocksize; writecount++)
- {
- retval = dap_queue_ap_write(dap, AP_REG_DRW,
- *(uint32_t *) ((void *) (buffer + 4 * writecount)));
- if (retval != ERROR_OK)
- break;
- }
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, (uint32_t*)buffer, blocksize);
+ if (retval != ERROR_OK)
+ break;
if ((retval = dap_run(dap)) == ERROR_OK)
{
@@ -401,7 +397,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
memcpy(&outvalue, buffer, sizeof(uint32_t));
retval = dap_queue_ap_write(dap,
- AP_REG_DRW, outvalue);
+ AP_REG_DRW, &outvalue, 1);
if (retval != ERROR_OK)
break;
@@ -439,7 +435,7 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
- retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, &outvalue, 1);
if (retval != ERROR_OK)
break;
@@ -509,7 +505,7 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
memcpy(&outvalue, buffer, sizeof(uint32_t));
retval = dap_queue_ap_write(dap,
- AP_REG_DRW, outvalue);
+ AP_REG_DRW, &outvalue, 1);
if (retval != ERROR_OK)
break;
@@ -545,7 +541,7 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count,
if (retval != ERROR_OK)
return retval;
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
- retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, &outvalue, 1);
if (retval != ERROR_OK)
break;
@@ -561,13 +557,6 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count,
return retval;
}
-/* FIXME don't import ... this is a temporary workaround for the
- * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
- */
-extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
- uint8_t instr, uint8_t reg_addr, uint8_t RnW,
- uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
-
/**
* Synchronously read a block of 32-bit words into a buffer
* @param dap The DAP connected to the MEM-AP.
@@ -606,39 +595,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
- /* FIXME remove these three calls to adi_jtag_dp_scan(),
- * so this routine becomes transport-neutral. Be careful
- * not to cause performance problems with JTAG; would it
- * suffice to loop over dap_queue_ap_read(), or would that
- * be slower when JTAG is the chosen transport?
- */
-
- /* Scan out first read */
- retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
- DPAP_READ, 0, NULL, NULL);
- if (retval != ERROR_OK)
- return retval;
- for (readcount = 0; readcount < blocksize - 1; readcount++)
- {
- /* Scan out next read; scan in posted value for the
- * previous one. Assumes read is acked "OK/FAULT",
- * and CTRL_STAT says that meant "OK".
- */
- retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
- DPAP_READ, 0, buffer + 4 * readcount,
- &dap->ack);
- if (retval != ERROR_OK)
- return retval;
- }
-
- /* Scan in last posted value; RDBUFF has no other effect,
- * assuming ack is OK/FAULT and CTRL_STAT says "OK".
- */
- retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
- DPAP_READ, 0, buffer + 4 * readcount,
- &dap->ack);
- if (retval != ERROR_OK)
- return retval;
+ dap_queue_ap_read(dap, AP_REG_DRW, (uint32_t*)buffer, blocksize);
retval = dap_run(dap);
if (retval != ERROR_OK)
@@ -708,7 +665,10 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
do
{
- retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ /* TODO: read first the whole memory and convert after.
+ * This may increase the performance
+ */
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue, 1);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
@@ -756,7 +716,7 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue, 1);
if (retval != ERROR_OK)
break;
@@ -818,7 +778,7 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
do
{
- retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue, 1);
if (retval != ERROR_OK)
return retval;
if ((retval = dap_run(dap)) != ERROR_OK)
@@ -866,7 +826,7 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@@ -1008,7 +968,11 @@ int ahbap_debugport_init(struct adiv5_dap *dap)
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ if (dap->ops->is_swd){
+ retval = dap_queue_dp_write(dap, DP_ABORT, DAPABORT | STKERRCLR | STKCMPCLR | WDERRCLR | ORUNERRCLR);
+ }else{
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
+ }
if (retval != ERROR_OK)
return retval;
@@ -1097,10 +1061,10 @@ int dap_get_debugbase(struct adiv5_dap *dap, int ap,
ap_old = dap->ap_current;
dap_ap_select(dap, ap);
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase, 1);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@@ -1632,7 +1596,7 @@ COMMAND_HANDLER(dap_baseaddr_command)
* though they're not common for now. This should
* use the ID register to verify it's a MEM-AP.
*/
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@@ -1696,7 +1660,7 @@ COMMAND_HANDLER(dap_apsel_command)
dap->apsel = apsel;
dap_ap_select(dap, apsel);
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@@ -1734,7 +1698,7 @@ COMMAND_HANDLER(dap_apid_command)
dap_ap_select(dap, apsel);
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid, 1);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 1c08547..311c294 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -212,10 +212,10 @@ struct dap_ops {
/** AP register read. */
int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
- uint32_t *data);
+ uint32_t *data, uint32_t size);
/** AP register write. */
int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
- uint32_t data);
+ uint32_t *data, uint32_t size);
/** AP operation abort. */
int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
@@ -289,10 +289,10 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_read(struct adiv5_dap *dap,
- unsigned reg, uint32_t *data)
+ unsigned reg, uint32_t *data, uint32_t count)
{
assert(dap->ops != NULL);
- return dap->ops->queue_ap_read(dap, reg, data);
+ return dap->ops->queue_ap_read(dap, reg, data, count);
}
/**
@@ -305,10 +305,10 @@ static inline int dap_queue_ap_read(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_write(struct adiv5_dap *dap,
- unsigned reg, uint32_t data)
+ unsigned reg, uint32_t *data, uint32_t count)
{
assert(dap->ops != NULL);
- return dap->ops->queue_ap_write(dap, reg, data);
+ return dap->ops->queue_ap_write(dap, reg, data, count);
}
/**
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 98a775c..e86aeea 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -70,6 +70,7 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
{
int retval;
uint32_t dcrdr;
+ uint32_t outval = regnum;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
@@ -82,7 +83,7 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
+ retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), &outval, 1);
if (retval != ERROR_OK)
return retval;
@@ -90,7 +91,7 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+ retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value, 1);
if (retval != ERROR_OK)
return retval;
@@ -110,7 +111,7 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
uint32_t value, int regnum)
{
int retval;
- uint32_t dcrdr;
+ uint32_t dcrdr, outval;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
@@ -123,14 +124,15 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+ retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), &value, 1);
// XXX check retval
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
+ outval = regnum | DCRSR_WnR;
+ retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), &outval, 1);
// XXX check retval
retval = dap_run(swjdp);
------------------------------------------------------------------------------
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