This is an automated email from Gerrit.
Akos Vandra (axo...@gmail.com) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/676
-- gerrit
commit abcd7ec728ed0ae1925711981114adc340f9f0dc
Author: Vandra Akos <axo...@gmail.com>
Date: Sun May 27 12:50:04 2012 +0200
added target configs for the lpc17xx devices
lpc1751, lpc1752, lpc1754, lpc1756, lpc1758, lpc1759
lpc1763, lpc1764, lpc1765, lpc1766, lpc1767, lpc1768, lpc1769
Change-Id: I740b66930cd379c9390f3c1031cdbada747a6ce4
Signed-off-by: Vandra Akos <axo...@gmail.com>
diff --git a/tcl/target/lpc1751.cfg b/tcl/target/lpc1751.cfg
new file mode 100644
index 0000000..1286c10
--- /dev/null
+++ b/tcl/target/lpc1751.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1751
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x2000
+set CPUROMSIZE 0x8000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1752.cfg b/tcl/target/lpc1752.cfg
new file mode 100644
index 0000000..5fa2a65
--- /dev/null
+++ b/tcl/target/lpc1752.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1752
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x10000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1754.cfg b/tcl/target/lpc1754.cfg
new file mode 100644
index 0000000..0841f23
--- /dev/null
+++ b/tcl/target/lpc1754.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1754
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x20000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1756.cfg b/tcl/target/lpc1756.cfg
new file mode 100644
index 0000000..9e2f48a
--- /dev/null
+++ b/tcl/target/lpc1756.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1756
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1758.cfg b/tcl/target/lpc1758.cfg
new file mode 100644
index 0000000..edcda07
--- /dev/null
+++ b/tcl/target/lpc1758.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1758
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1759.cfg b/tcl/target/lpc1759.cfg
new file mode 100644
index 0000000..b308c8a
--- /dev/null
+++ b/tcl/target/lpc1759.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1759
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1763.cfg b/tcl/target/lpc1763.cfg
new file mode 100644
index 0000000..82285e7
--- /dev/null
+++ b/tcl/target/lpc1763.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1763
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1764.cfg b/tcl/target/lpc1764.cfg
new file mode 100644
index 0000000..24728aa
--- /dev/null
+++ b/tcl/target/lpc1764.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1764
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x20000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1765.cfg b/tcl/target/lpc1765.cfg
new file mode 100644
index 0000000..d121661
--- /dev/null
+++ b/tcl/target/lpc1765.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1765
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1766.cfg b/tcl/target/lpc1766.cfg
new file mode 100644
index 0000000..e01c157
--- /dev/null
+++ b/tcl/target/lpc1766.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1766
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1767.cfg b/tcl/target/lpc1767.cfg
new file mode 100644
index 0000000..cb9c055
--- /dev/null
+++ b/tcl/target/lpc1767.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1767
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
diff --git a/tcl/target/lpc1769.cfg b/tcl/target/lpc1769.cfg
new file mode 100644
index 0000000..4c3158e
--- /dev/null
+++ b/tcl/target/lpc1769.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1768
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--
------------------------------------------------------------------------------
Live Security Virtual Conference
Exclusive live event will cover all the ways today's security and
threat landscape has changed and how IT managers can respond. Discussions
will include endpoint security, mobile security and the latest in malware
threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
_______________________________________________
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel
