This is an automated email from Gerrit.
Akos Vandra (axo...@gmail.com) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/674
-- gerrit
commit f77f8d0d099a86c10638b3eed3058b86d80ae5c0
Author: Vandra Akos <axo...@gmail.com>
Date: Sun May 27 12:15:21 2012 +0200
lpc1768.cfg pulled out constans from flash init as variables
Seems like an esthetic change, but it will allow easy support for
other lpc17xx devices.
Change-Id: I2cb953ce1afdd82f6ca65b38d5557a28416f895e
Signed-off-by: Vandra Akos <axo...@gmail.com>
diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index d1734dd..8bcab9b 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -22,12 +22,25 @@ if { [info exists CCLK] } {
} else {
set _CCLK 4000
}
+
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
+if { [info exists CPURAMSIZE] } {
+ set _CPURAMSIZE $CPURAMSIZE
+} else {
+ set _CPURAMSIZE 0x8000
+}
+
+if { [info exists CPUROMSIZE] } {
+ set _CPUROMSIZE $CPUROMSIZE
+} else {
+ set _CPUROMSIZE 0x80000
+}
+
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
@@ -40,13 +53,13 @@ target create $_TARGETNAME cortex_m3 -chain-position
$_TARGETNAME
# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
# LPC1768 has 512kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock>
[calc checksum]
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
+flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# Run with *real slow* clock by default since the
--
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