I'm trying to debug an application running on an Atmel SAM3U which goes into sleep mode using "wfi" and only wakes up occasionally on timer overflows, etc...
Access to the JTAG Debug Port (JTAG-DP) seems to work while in sleep mode. However, accessing the control and status register (DHCSR) of the debug core fails and causes a STICKYERR in the CTRL/STAT register of the JTAG-DP. According to the Cortex-M3 TRM (Section 7.2.1) the processor clock (HCLK) is disabled while in sleep mode until an interrupt occurs (clock gating). The following issue on the bug tracker (http://sourceforge.net/apps/trac/openocd/ticket/28) suggests that a power-up signal should be generated by the debugger to wake-up the core, however, it seems that the corresponding bits in the CTRL/STAT register (CDBGPWRUPREQ and CSYSPWRUPREQ) of the JTAG-DP are already set when the debug port is initialized by openocd. Is there any other way to wake-up the processor through the JTAG-DP while in sleep mode? Regards, Philipp ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
