On 26/07/2012 09:00, Philipp Sommer wrote:
> I'm trying to debug an application running on an Atmel SAM3U which
> goes into sleep mode using "wfi" and only wakes up occasionally on
> timer overflows, etc...
>
> Access to the JTAG Debug Port (JTAG-DP) seems to work while in sleep
> mode. However, accessing the control and status register (DHCSR) of
> the debug core fails and causes a STICKYERR in the CTRL/STAT register
> of the JTAG-DP. According to the Cortex-M3 TRM (Section 7.2.1) the
> processor clock (HCLK) is disabled while in sleep mode until an
> interrupt occurs (clock gating).
>
> The following issue on the bug tracker
> (http://sourceforge.net/apps/trac/openocd/ticket/28) suggests that a
> power-up signal should be generated by the debugger to wake-up the
> core, however, it seems that the corresponding bits in the CTRL/STAT
> register (CDBGPWRUPREQ and CSYSPWRUPREQ) of the JTAG-DP are already
> set when the debug port is initialized by openocd.
>
> Is there any other way to wake-up the processor through the JTAG-DP
> while in sleep mode?
>
> Regards,
> Philipp
>

Support for this is a bit hit and miss, depending on target and 
sometimes OpenOCD version.

Some targets (STM32) have specific support for low power debugging that 
help in this situation.

Not sure about the SAM3 parts, afraid i have always found disabling the 
wfi while debugging is the best option.

This problems does not just effect OpenOCD however, i have commercial 
tools at work that also suffer when trying to debug wfi.

Cheers
Spen


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