This is an automated email from Gerrit. Ivan Sergeev (vserg...@gmail.com) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1896
-- gerrit commit ec8e714122892dd84383935eb60ebc5f48c49f80 Author: Vanya Sergeev <vserg...@gmail.com> Date: Thu Jan 23 10:58:48 2014 -0800 cfg: add lpc1114 / lpc11xx targets Flashing and debugging tested on a LPC1114 target with a ST-Link v2 interface. Change-Id: I4e2a437563054bd0bda7ab4d180053ed67a07dc4 Signed-off-by: Vanya Sergeev <vserg...@gmail.com> diff --git a/tcl/target/lpc1114.cfg b/tcl/target/lpc1114.cfg new file mode 100644 index 0000000..1799635 --- /dev/null +++ b/tcl/target/lpc1114.cfg @@ -0,0 +1,22 @@ +# NXP LPC1114 Cortex-M0 +set CHIPNAME lpc1114 +set CPUTAPID 0x0bb11477 + +if { ![info exists CPUROMSIZE] } { + error "CPUROMSIZE is not set. The LPC1114 part is available in many Flash and SRAM size configurations. Please set CPUROMSIZE before including this configuration file." +} +if { ![info exists CPURAMSIZE] } { + error "CPURAMSIZE is not set. The LPC1114 part is available in many Flash and SRAM size configurations. Please set CPURAMSIZE before including this configuration file." +} + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 12000 + +# Include the main configuration file. +source [find lpc11xx.cfg]; diff --git a/tcl/target/lpc11xx.cfg b/tcl/target/lpc11xx.cfg new file mode 100644 index 0000000..c5dca53 --- /dev/null +++ b/tcl/target/lpc11xx.cfg @@ -0,0 +1,97 @@ +# Main file for NXP LPC11xx Cortex-M0 +# +# !!!!!! +# +# This file should not be included directly, rather +# by the lpc1112.cfg, lpc1114.cfg, etc. which set the +# needed variables to the appropriate values. +# +# !!!!!! + +# LPC11xx chips support only SWD transports. +# Source swj-dp for generic swj_newdap. +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + error "_CHIPNAME not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." +} + +# After reset the chip is clocked by the ~12MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +if { [info exists CCLK] } { + set _CCLK $CCLK +} else { + set _CCLK 12000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + error "_CPUTAPID not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." +} + +if { [info exists CPURAMSIZE] } { + set _CPURAMSIZE $CPURAMSIZE +} else { + error "_CPURAMSIZE not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." +} + +if { [info exists CPUROMSIZE] } { + set _CPUROMSIZE $CPUROMSIZE +} else { + error "_CPUROMSIZE not set. Please do not include lpc11xx.cfg directly, but the specific chip configuration file (lpc1112.cfg, lpc1114.cfg, etc)." +} + +if { [info exists TRANSPORT] } { + set _TRANSPORT $TRANSPORT +} else { + # Default to the SWD transport used by ST-Link v2. + set _TRANSPORT hla_swd +} + +transport select $_TRANSPORT + +if { $_TRANSPORT == "hla_swd" } { + hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID + set _TARGETTYPE hla_target +} else { + swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID + set _TARGETTYPE cortex_m +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME + +# The LPC11xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) +$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE + +# The LPC11xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code +# (including a boot loader which verifies the flash exception table's checksum). +# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \ + lpc1700 $_CCLK calc_checksum + +$_TARGETNAME configure -event reset-init { + # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select + # "User Flash Mode" where interrupt vectors are _not_ remapped, + # and reside in flash instead). + # + # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description + # Bit Symbol Value Description + # 1:0 MAP System memory remap + # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. + # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM. + # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. + # 31:2 - - Reserved. + + mww 0x40048000 0x02 +} + -- ------------------------------------------------------------------------------ CenturyLink Cloud: The Leader in Enterprise Cloud Services. Learn Why More Businesses Are Choosing CenturyLink Cloud For Critical Workloads, Development Environments & Everything In Between. Get a Quote or Start a Free Trial Today. http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel