Re: [OpenOCD-devel] NXP LPC81x support?

Andreas Ortmann Sat, 10 May 2014 01:01:22 -0700

Hi,

On 08.05.2014 19:34, Tim Wescott wrote:

Based on some comments in the release notes about flash support for the
LPC800 and LPC810, I was hoping that these chips would also be supported
for debugging.


I just finished building and installing OpenOCD 0.8.0, hoping that there
would be a target file for the LPC81x.

To my disappointment, I didn't see any.

How much support is there for this chip?  Might it be possible for me to
cobble together a configuration file for the LPC811M00 as a target?

I can get debug access to LPC810 & LPC812 with st-linkv2 and theattached scripts.


They are based on (copied from)
https://gist.github.com/RickKimball/9009480.

I want (of course) debugging and flash programming.

TIA

Greetings,
Andreas Ortmann

#--------------------------------------------------------
# Main file for NXP LPC8xx Cortex-M0+
#
# !!!!!!
#
# This file should not be included directly, rather
# needed variables to the appropriate values.
#
# !!!!!!

# Source swj-dp for generic swj_newdap.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
} else {
        error "_CHIPNAME not set. Please do not include lpc8xx.cfg directly, 
but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
if { [info exists CCLK] } {
        set _CCLK $CCLK
} else {
        set _CCLK 12000
}

if { [info exists CPUTAPID] } {
        set _CPUTAPID $CPUTAPID
} else {
        error "_CPUTAPID not set. Please do not include lpc8xx.cfg directly, 
but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists CPURAMSIZE] } {
        set _CPURAMSIZE $CPURAMSIZE
} else {
        error "_CPURAMSIZE not set. Please do not include lpc8xx.cfg directly, 
but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists CPUROMSIZE] } {
        set _CPUROMSIZE $CPUROMSIZE
} else {
        error "_CPUROMSIZE not set. Please do not include lpc8xx.cfg directly, 
but the specific chip configuration file (lpc812.cfg, lpc811.cfg, etc)."
}

if { [info exists TRANSPORT] } {
        set _TRANSPORT $TRANSPORT
} else {
        # Default to the SWD transport used by ST-Link v2.
        set _TRANSPORT hla_swd
}

transport select $_TRANSPORT

if { $_TRANSPORT == "hla_swd" } {
        hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
        set _TARGETTYPE hla_target
} else {
        swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
        set _TARGETTYPE cortex_m
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME $_TARGETTYPE -chain-position $_TARGETNAME

# The LPC8xx devices have 1/2/4kB of SRAM in the ARMv7-M "Code" area (at 
0x10000000)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE

# The LPC8xx devices have 4/8/16kB of flash memory, managed by ROM code
# (including a boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc 
checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc800 $_CCLK 
calc_checksum

$_TARGETNAME configure -event reset-init {
    mww 0x40048000 0x02
}

$_TARGETNAME configure -event gdb-attach {
    reset halt
}

$_TARGETNAME configure -event gdb-detach {
    resume
}

#-----------------------------------------
# NXP lpc812 Cortex-M0+ 16k flash, 4k ram

set CHIPNAME lpc812
set CPUTAPID 0x0bc11477
set CPUROMSIZE 0x4000
set CPURAMSIZE 0x1000
set WORKAREASIZE 4096

# After reset the chip is clocked by the ~12MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
#
# CCLK is the core clock frequency in KHz
set CCLK 12000

# Include the main configuration file.
source [find lpc8xx.cfg];

#
# debug812.cfg
# openocd -s . -f debug812.cfg

source [find interface/stlink-v2.cfg]
source [find lpc812.cfg]

init
reset init

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