This is an automated email from Gerrit.
Burlacu Cornel (rody...@yahoo.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/2373
-- gerrit
commit ced7937798c61e29068785a3f124e9423863f7bf
Author: cornelus <rody...@yahoo.com>
Date: Mon Nov 3 13:17:34 2014 +0200
Support for lantiq bassed device.
Change-Id: Id4b70252938ccf06141bba5676e57604c22a1236
Signed-off-by: cornelus <rody...@yahoo.com>
diff --git a/testing/lantiq/board/easy50712.cfg
b/testing/lantiq/board/easy50712.cfg
new file mode 100644
index 0000000..0535dcb
--- /dev/null
+++ b/testing/lantiq/board/easy50712.cfg
@@ -0,0 +1,26 @@
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x4000000 2 2 $TARGETNAME
+
+proc easy50712_mc_init {} {
+ echo "EASY50712: MC setup"
+}
+
+proc easy50712_reset_init {} {
+ echo "EASY50712: reset init"
+ danube_cgu_init
+ danube_mc_init_prepare
+ easy50712_mc_init
+ danube_mc_init_finish
+ danube_ebu_init
+}
+
+$TARGETNAME configure -event reset-init { easy50712_reset_init }
+
+proc easy50712_ramboot {} {
+ echo "EASY50712: reset init"
+ reset init
+
+ set loadaddr 0xa0100000
+ load_image easy50712_ram/u-boot.bin $loadaddr bin
+ resume $loadaddr
+}
diff --git a/testing/lantiq/board/easy80920.cfg
b/testing/lantiq/board/easy80920.cfg
new file mode 100644
index 0000000..b7d8795
--- /dev/null
+++ b/testing/lantiq/board/easy80920.cfg
@@ -0,0 +1,26 @@
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x4000000 2 2 $TARGETNAME
+
+proc easy80920_mc_init {} {
+ echo "EASY80920: MC setup"
+}
+
+proc easy80920_reset_init {} {
+ echo "EASY80920: reset init"
+ vrx200_hrst
+ vrx200_cgu_init
+ vrx200_mc_init_prepare
+ easy80920_mc_init
+ vrx200_mc_init_finish
+}
+
+$TARGETNAME configure -event reset-init { easy80920_reset_init }
+
+proc easy80920_ramboot {} {
+ echo "EASY80920: reset init"
+ reset init
+
+ set loadaddr 0x80100000
+ load_image easy80920_ram/u-boot.bin $loadaddr bin
+ resume $loadaddr
+}
diff --git a/testing/lantiq/board/p661hnu.cfg b/testing/lantiq/board/p661hnu.cfg
new file mode 100644
index 0000000..abf97fb
--- /dev/null
+++ b/testing/lantiq/board/p661hnu.cfg
@@ -0,0 +1,76 @@
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x4000000 2 2 $TARGETNAME
+
+proc p661hnu_mc_init {} {
+ echo "p661hnu: MC setup"
+
+ arx100_mc_init_prepare
+
+ mww 0xbf801000 0x1b1b
+ mww 0xbf801010 0x0
+ mww 0xbf801020 0x0
+ mww 0xbf801030 0x0
+ mww 0xbf801040 0x0
+ mww 0xbf801050 0x200
+ mww 0xbf801060 0x306
+ mww 0xbf801070 0x303
+ mww 0xbf801080 0x102
+ mww 0xbf801090 0x70a
+ mww 0xbf8010a0 0x203
+ mww 0xbf8010b0 0xc02
+ mww 0xbf8010c0 0x1c8
+ mww 0xbf8010d0 0x1
+ mww 0xbf8010e0 0x0
+ mww 0xbf8010f0 0x144
+ mww 0xbf801100 0xC800
+ mww 0xbf801110 0xd
+ mww 0xbf801120 0x301
+ mww 0xbf801130 0x200
+ mww 0xbf801140 0xa03
+ mww 0xbf801150 0x1900
+ mww 0xbf801160 0x1919
+ mww 0xbf801170 0x0
+ mww 0xbf801180 0x66
+ mww 0xbf801190 0x0
+ mww 0xbf8011a0 0x0
+ mww 0xbf8011b0 0x0
+ mww 0xbf8011c0 0x50a
+ mww 0xbf8011d0 0x2d65
+ mww 0xbf8011e0 0x81b1
+ mww 0xbf8011f0 0x0
+ mww 0xbf801200 0x0
+ mww 0xbf801210 0x0
+ mww 0xbf801220 0x0
+ mww 0xbf801230 0x0
+ mww 0xbf801240 0x0
+ mww 0xbf801250 0x0
+ mww 0xbf801260 0x0
+ mww 0xbf801270 0x0
+ mww 0xbf801280 0x0
+ mww 0xbf801290 0x0
+ mww 0xbf8012a0 0x0
+ mww 0xbf8012b0 0x0
+ mww 0xbf8012c0 0x0
+ mww 0xbf8012d0 0x600
+ mww 0xbf8012e0 0x0
+
+ arx100_mc_init_finish
+}
+
+proc p661hnu_reset_init {} {
+ echo "p661hnu: reset init"
+
+ arx100_cgu_init
+ p661hnu_mc_init
+}
+
+$TARGETNAME configure -event reset-init { p661hnu_reset_init }
+
+proc p661hnu_ramboot {} {
+ reset init
+
+ set loadaddr 0xa0100000
+ echo "p661hnu: loading u-boot.bin to $loadaddr"
+ load_image p661hnufx_ram/u-boot.bin $loadaddr bin
+ resume $loadaddr
+}
diff --git a/testing/lantiq/board/vgv7519.cfg b/testing/lantiq/board/vgv7519.cfg
new file mode 100644
index 0000000..1fc1ec3
--- /dev/null
+++ b/testing/lantiq/board/vgv7519.cfg
@@ -0,0 +1,30 @@
+# The VGV7519 has a DUAL-nor flash configuration
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x00800000 2 2 $TARGETNAME
+set FLASHNAME $CHIPNAME.nor1
+flash bank $FLASHNAME cfi 0xb4000000 0x00800000 2 2 $TARGETNAME
+
+proc vgv7519_mc_init {} {
+ echo "VGV7519: MC setup"
+}
+
+proc vgv7519_reset_init {} {
+ echo "VGV7519: reset init"
+ vrx200_hrst
+ vrx200_cgu_init
+ vrx200_mc_init_prepare
+ vgv7519_mc_init
+ vrx200_mc_init_finish
+}
+
+$TARGETNAME configure -event reset-init { vgv7519_reset_init }
+
+# Load a ram version of u-boot
+proc vgv7519_uboot_ram {} {
+ echo "VGV7519: reset init"
+ reset init
+
+ set loadaddr 0x80100000
+ load_image u-boot.bin $loadaddr bin
+ resume $loadaddr
+}
diff --git a/testing/lantiq/openocd.cfg b/testing/lantiq/openocd.cfg
new file mode 100644
index 0000000..3822c6c
--- /dev/null
+++ b/testing/lantiq/openocd.cfg
@@ -0,0 +1,37 @@
+source [find interface/usb-jtag.cfg]
+#source [find interface/altera-usb-blaster.cfg]
+
+#adapter_khz 0
+
+#source [find target/danube.cfg]
+source [find target/vrx200.cfg]
+
+#source [find board/easy50712.cfg]
+#source [find board/easy80920.cfg]
+source [find board/vgv7519.cfg]
+
+gdb_flash_program enable
+#gdb_flash_program disable
+gdb_memory_map enable
+#gdb_memory_map disable
+gdb_breakpoint_override hard
+
+proc flash_init {} {
+ echo "vrx200: flash_init"
+
+ reset halt
+ vrx200_ebu_init
+ vrx200_ebu_swap_enable
+ flash probe 0
+}
+
+proc flash_deinit {} {
+ vrx200_ebu_swap_disable
+ echo "vrx200: flashing done"
+}
+
+proc flash_file {filename} {
+ flash_init
+ flash write_image erase $filename 0xb0000000
+ flash_deinit
+}
diff --git a/testing/lantiq/target/arx100.cfg b/testing/lantiq/target/arx100.cfg
new file mode 100644
index 0000000..9f3408b
--- /dev/null
+++ b/testing/lantiq/target/arx100.cfg
@@ -0,0 +1,85 @@
+reset_config trst_only
+#adapter_nsrst_assert_width 100
+adapter_nsrst_delay 100
+#jtag_ntrst_assert_width 100
+jtag_ntrst_delay 100
+
+set CHIPNAME arx100
+jtag newtap $CHIPNAME cpu0 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x1183
+jtag newtap $CHIPNAME cpu1 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x183
+
+set TARGETNAME $CHIPNAME.cpu1
+target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x4000000 2 2 $TARGETNAME
+
+$TARGETNAME configure -work-area-phys 0x1e1a0000 -work-area-size 0x10000
-work-area-backup 0
+
+proc arx100_cgu_init {} {
+ echo "ARX100: CGU init"
+
+ # CGU for CPU 333Mhz, DDR 167Mhz
+ mww 0xbf103010 0x80
+
+ # CGU update
+ mww 0xBF103014 0x01
+}
+
+proc arx100_mc_init_prepare {} {
+ echo "ARX100: MC init prepare"
+
+ # Clear error access log registers
+ mww 0xbf800010 0x0
+ mww 0xbf800020 0x0
+
+ # Enable FPI, DDR and SRAM module in memory controller
+ mww 0xbf800060 0xd
+
+ # Clear start bit of DDR memory controller
+ mww 0xbf801030 0x0
+
+ # DDR Register
+
+}
+
+proc arx100_mc_init_finish {} {
+ echo "ARX100: MC init finish"
+
+ # Set start bit of DDR memory controller
+ mww 0xbf801030 0x100
+
+ # wait for DLL lock
+ sleep 200
+}
+
+proc arx100_ebu_init {} {
+ echo "ARX100: EBU init"
+
+ mww 0xbe105360 0x0001f7ff
+ mww 0xbe105320 0x10000011
+}
+
+proc arx100_ebu_swap_enable {} {
+ echo "ARX100: EBU swap enable"
+
+ mww 0xbe105360 0x4001f7ff
+}
+
+proc arx100_ebu_swap_disable {} {
+ echo "ARX100: EBU swap disable"
+
+ mww 0xbe105360 0x0001f7ff
+}
+
+proc arx100_gdb_attach {} {
+ echo "ARX100: gdb-attach"
+
+ reset halt
+ arx100_ebu_init
+ #arx100_ebu_swap_enable
+ #flash probe 0
+ #arx100_ebu_swap_disable
+}
+
+$TARGETNAME configure -event gdb-attach { arx100_gdb_attach }
diff --git a/testing/lantiq/target/danube.cfg b/testing/lantiq/target/danube.cfg
new file mode 100644
index 0000000..1c8a52b
--- /dev/null
+++ b/testing/lantiq/target/danube.cfg
@@ -0,0 +1,140 @@
+reset_config trst_and_srst
+#adapter_nsrst_assert_width 100
+adapter_nsrst_delay 100
+#jtag_ntrst_assert_width 100
+jtag_ntrst_delay 100
+
+set CHIPNAME danube
+jtag newtap $CHIPNAME cpu0 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x183
+jtag newtap $CHIPNAME cpu1 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x183
+
+set TARGETNAME $CHIPNAME.cpu1
+target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+
+set FLASHNAME $CHIPNAME.nor0
+flash bank $FLASHNAME cfi 0xb0000000 0x4000000 2 2 $TARGETNAME
+
+$TARGETNAME configure -work-area-phys 0x1e1a0000 -work-area-size 0x10000
-work-area-backup 0
+
+proc danube_cgu_init {} {
+ echo "Danube: CGU init"
+
+ # CGU for CPU 333Mhz, DDR 167Mhz, FPI 83Mhz
+ mww 0xbf103010 0x0e8
+ mww 0xbf103014 0x01
+ mww 0xbf103020 0x780000
+}
+
+proc danube_pmu_init {} {
+ echo "Danube: PMU init"
+
+ # Power-on all subsystems
+ mww 0xbf10201c 0x2F3FFE3
+}
+
+proc danube_mc_init_prepare {} {
+ echo "Danube: MC init prepare"
+
+ # General MC register
+ mww 0xbf800060 0x7
+ mww 0xbf800010 0x0
+ mww 0xbf800020 0x0
+ mww 0xbf800200 0x02
+ mww 0xbf800210 0x0
+
+ # DDR Register
+ mww 0xbf801000 0x1b1b
+ mww 0xbf801010 0x0
+ mww 0xbf801020 0x0
+ mww 0xbf801030 0x0
+ mww 0xbf801040 0x0
+ mww 0xbf801050 0x200
+ mww 0xbf801060 0x0605
+ mww 0xbf801070 0x303
+ mww 0xbf801080 0x102
+ mww 0xbf801090 0x70a
+ mww 0xbf8010a0 0x203
+ mww 0xbf8010b0 0xc02
+ mww 0xbf8010c0 0x1c8
+ mww 0xbf8010d0 0x1
+ mww 0xbf8010e0 0x0
+ mww 0xbf8010f0 0x13c
+ mww 0xbf801100 0xC800
+ mww 0xbf801110 0xd
+ mww 0xbf801120 0x300
+ mww 0xbf801130 0x200
+ mww 0xbf801140 0xa04
+ mww 0xbf801150 0xd00
+ mww 0xbf801160 0xd0d
+ mww 0xbf801170 0x0
+ mww 0xbf801180 0x062
+ mww 0xbf801190 0x0
+ mww 0xbf8011a0 0x0
+ mww 0xbf8011b0 0x0
+ mww 0xbf8011c0 0x510
+ mww 0xbf8011d0 0x2d89
+ mww 0xbf8011e0 0x8300
+ mww 0xbf8011f0 0x0
+ mww 0xbf801200 0x0
+ mww 0xbf801210 0x0
+ mww 0xbf801220 0x0
+ mww 0xbf801230 0x0
+ mww 0xbf801240 0x0
+ mww 0xbf801250 0x0
+ mww 0xbf801260 0x0
+ mww 0xbf801270 0x0
+ mww 0xbf801280 0x0
+ mww 0xbf801290 0x0
+ mww 0xbf8012a0 0x0
+ mww 0xbf8012b0 0x0
+ mww 0xbf8012c0 0x0
+ mww 0xbf8012d0 0x500
+ mww 0xbf8012e0 0x0
+}
+
+proc danube_mc_init_finish {} {
+ echo "Danube: MC init finish"
+
+ # start MC
+ mww 0xbf800060 0x05
+ mww 0xbf801030 0x100
+
+ # wait for DLL lock
+ sleep 50
+}
+
+proc danube_ebu_init {} {
+ echo "Danube: EBU init"
+
+ mww 0xbe105360 0x0001f7ff
+ mww 0xbe105320 0x10000011
+}
+
+proc danube_ebu_swap_enable {} {
+ echo "Danube: EBU swap enable"
+
+ mww 0xbe105360 0x4001f7ff
+}
+
+proc danube_ebu_swap_disable {} {
+ echo "Danube: EBU swap disable"
+
+ mww 0xbe105360 0x0001f7ff
+}
+
+proc danube_flash_probe {} {
+ danube_ebu_swap_enable
+ sleep 10
+ flash probe 0
+ danube_ebu_swap_disable
+}
+
+proc danube_gdb_attach {} {
+ echo "Danube: gdb-attach"
+
+ reset halt
+ danube_ebu_init
+ danube_flash_probe
+}
+
+$TARGETNAME configure -event gdb-attach { danube_gdb_attach }
diff --git a/testing/lantiq/target/vrx200.cfg b/testing/lantiq/target/vrx200.cfg
new file mode 100644
index 0000000..a0c910a
--- /dev/null
+++ b/testing/lantiq/target/vrx200.cfg
@@ -0,0 +1,164 @@
+reset_config trst_only
+#adapter_nsrst_assert_width 100
+adapter_nsrst_delay 100
+#jtag_ntrst_assert_width 100
+jtag_ntrst_delay 100
+
+set CHIPNAME vrx200
+jtag newtap $CHIPNAME cpu0 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x1183
+jtag newtap $CHIPNAME cpu1 -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id
0x183
+
+set TARGETNAME $CHIPNAME.cpu1
+target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+
+$TARGETNAME configure -work-area-phys 0x1e220000 -work-area-size 0x10000
-work-area-backup 0
+
+proc vrx200_cgu_init {} {
+ echo "VRX200: CGU init"
+
+ # CGU for speed 500/250
+ mww 0xBF10300c 0x12
+ mww 0xBF103010 0x03020000
+
+ # CGU update
+ mww 0xBF103020 0x01
+}
+
+proc vrx200_mc_init_prepare {} {
+ echo "VRX200: MC init prepare"
+
+ # halt MC
+ mww 0xBF401070 0x0
+
+ # programm MC settings
+ mww 0xBF401000 0x101
+ mww 0xBF401010 0x1000100
+ mww 0xBF401020 0x1010000
+ mww 0xBF401030 0x100
+ mww 0xBF401040 0x1000000
+ mww 0xBF401050 0x1000101
+ mww 0xBF401060 0x1000100
+ mww 0xBF401070 0x1010000
+ mww 0xBF401080 0x1000101
+ mww 0xBF401090 0x0
+ mww 0xBF4010A0 0x2000100
+ mww 0xBF4010B0 0x2000401
+ mww 0xBF4010C0 0x30000
+ mww 0xBF4010D0 0x202
+ mww 0xBF4010E0 0x7080A0F
+ mww 0xBF4010F0 0x2040F
+ mww 0xBF401100 0x40000
+ mww 0xBF401110 0x70102
+ mww 0xBF401120 0x4020002
+ mww 0xBF401130 0x30302
+ mww 0xBF401140 0x8000700
+ mww 0xBF401150 0x40F020A
+ mww 0xBF401160 0x0
+ mww 0xBF401170 0xC020000
+ mww 0xBF401180 0x4401B04
+ mww 0xBF401190 0x0
+ mww 0xBF4011A0 0x0
+ mww 0xBF4011B0 0x6420000
+ mww 0xBF4011C0 0x0
+ mww 0xBF4011D0 0x0
+ mww 0xBF4011E0 0x798
+ mww 0xBF4011F0 0x0
+ mww 0xBF401200 0x0
+ mww 0xBF401210 0x650000
+ mww 0xBF401220 0x200C8
+ mww 0xBF401230 0x1D445D
+ mww 0xBF401240 0xC8
+ mww 0xBF401250 0xC351
+ mww 0xBF401260 0x0
+ mww 0xBF401270 0x141F04
+ mww 0xBF401280 0x142704
+ mww 0xBF401290 0x141b42
+ mww 0xBF4012A0 0x141b42
+ mww 0xBF4012B0 0x566504
+ mww 0xBF4012C0 0x566504
+ mww 0xBF4012D0 0x565F17
+ mww 0xBF4012E0 0x565F17
+ mww 0xBF4012F0 0x0
+ mww 0xBF401300 0x0
+ mww 0xBF401310 0x0
+ mww 0xBF401320 0x0
+ mww 0xBF401330 0x0
+ mww 0xBF401340 0x133
+ mww 0xBF401350 0xF3014B27
+ mww 0xBF401360 0xF3014B27
+ mww 0xBF401370 0xF3014B27
+ mww 0xBF401380 0xF3014B27
+ mww 0xBF401390 0x7C00301
+ mww 0xBF4013A0 0x7C00301
+ mww 0xBF4013B0 0x7C00301
+ mww 0xBF4013C0 0x7C00301
+ mww 0xBF4013D0 0x4
+}
+
+proc vrx200_mc_init_finish {} {
+ echo "VRX200: MC init finish"
+
+ # start MC
+ mww 0xBF401070 0x1010100
+
+ # wait for DLL lock
+ sleep 200
+}
+
+proc vrx200_ebu_init {} {
+ echo "VRX200: EBU init"
+
+# Single flash configuration
+ #mww 0xbe105360 0x0001f7ff
+ #mww 0xbe105320 0x10000011
+
+# Dual flash configuration
+ mww 0xbe105360 0x0001e7ff
+ mww 0xbe105320 0x10000031
+ mww 0xbe105364 0x0001e7ff
+ mww 0xbe105324 0x14000031
+}
+
+proc vrx200_ebu_swap_enable {} {
+ echo "VRX200: EBU swap enable"
+
+# Single flash configuration
+ #mww 0xbe105360 0x4001f7ff
+
+# Dual flash configuration
+ mww 0xbe105360 0x4001e7ff
+ mww 0xbe105364 0x4001e7ff
+}
+
+proc vrx200_ebu_swap_disable {} {
+ echo "VRX200: EBU swap disable"
+
+# Single flash configuration
+ #mww 0xbe105360 0x0001f7ff
+
+# Dual flash configuration
+ mww 0xbe105360 0x0001e7ff
+ mww 0xbe105364 0x0001e7ff
+}
+
+proc vrx200_hrst {} {
+ echo "VRX200: HRST"
+
+ # Assert HRST
+ mww 0xBF203010 0x21
+ sleep 800
+ mww 0xBF203010 0x20
+ sleep 10
+}
+
+proc vrx200_gdb_attach {} {
+ echo "VRX200: gdb-attach"
+
+ reset halt
+ vrx200_ebu_init
+ #vrx200_ebu_swap_enable
+ #flash probe 0
+ #vrx200_ebu_swap_disable
+}
+
+$TARGETNAME configure -event gdb-attach { vrx200_gdb_attach }
--
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