This is an automated email from Gerrit.
Paul Fertser (fercer...@gmail.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/2516
-- gerrit
commit 42896e15397b9a438e291b4f4acf188ccc935087
Author: Paul Fertser <fercer...@gmail.com>
Date: Thu Jan 29 13:58:45 2015 +0300
armv7m: do not access FPU registers when not present
This is runtime and valgrind tested with l0 and f3 hla boards.
Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23
Signed-off-by: Paul Fertser <fercer...@gmail.com>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index ee96f0e..58f500d 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -131,7 +131,7 @@ static const struct {
{ ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float",
"org.gnu.gdb.arm.vfp" },
};
-#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
+#define ARMV7M_NUM_REGS_FP ARRAY_SIZE(armv7m_regs)
/**
* Restores target context using the cache of core registers set up
@@ -148,7 +148,7 @@ int armv7m_restore_context(struct target *target)
if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
- for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
+ for (i = cache->num_regs - 1; i >= 0; i--) {
if (cache->reg_list[i].dirty) {
armv7m->arm.write_core_reg(target, &cache->reg_list[i],
i,
ARM_MODE_ANY,
cache->reg_list[i].value);
@@ -302,7 +302,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct
reg **reg_list[],
int i;
if (reg_class == REG_CLASS_ALL)
- *reg_list_size = ARMV7M_NUM_REGS;
+ *reg_list_size = armv7m->arm.core_cache->num_regs;
else
*reg_list_size = ARMV7M_NUM_CORE_REGS;
@@ -368,7 +368,7 @@ int armv7m_start_algorithm(struct target *target,
/* refresh core register cache
* Not needed if core register cache is always consistent with target
process state */
- for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) {
+ for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
armv7m_algorithm_info->context[i] = buf_get_u32(
armv7m->arm.core_cache->reg_list[i].value,
@@ -503,7 +503,7 @@ int armv7m_wait_algorithm(struct target *target,
}
}
- for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) {
+ for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
uint32_t regvalue;
regvalue =
buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i]) {
@@ -565,7 +565,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target
*target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct arm *arm = &armv7m->arm;
- int num_regs = ARMV7M_NUM_REGS;
+ int num_regs = ARMV7M_NUM_REGS_FP;
struct reg_cache **cache_p =
register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 761d95b..a15033e 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1877,6 +1877,11 @@ int cortex_m_examine(struct target *target)
armv7m->arm.is_armv6m = true;
}
+ if (armv7m->fp_feature != FPv4_SP) {
+ /* ignore unavailable FPU registers */
+ armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS
+ 6;
+ }
+
if (i == 4 || i == 3) {
/* Cortex-M3/M4 has 4096 bytes autoincrement range */
armv7m->dap.tar_autoincr_block = (1 << 12);
--
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