This is an automated email from Gerrit.
Paul Fertser (fercer...@gmail.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/2603
-- gerrit
commit 137fb0e1e47262d268cc4d3fea74541e226b0fa7
Author: Paul Fertser <fercer...@gmail.com>
Date: Sat Mar 14 08:15:12 2015 +0300
target/cortex_a: emit a clear error message when dbgbase can't be detected
In some cases (the most obvious are TI's SoCs) ROM table lacks entries
for the cores, so OpenOCD has no way to determine what debug base to
use. Due to an error fixed in ec9ccaa28849 it wasn't handled properly,
and OpenOCD would continue to try using dbgbase = 0, which happened to
work for e.g. AM437x.
This patch adds a clear indication to the user that to access such a
target, dbgbase must be set manually in the config.
Reported by Felipe Balbi on IRC.
Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298
Signed-off-by: Paul Fertser <fercer...@gmail.com>
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 9ae0432..33451fa 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2871,8 +2871,10 @@ static int cortex_a_examine_first(struct target *target)
/* Lookup 0x15 -- Processor DAP */
retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15,
&armv7a->debug_base, &coreidx);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Can not detect %s's dbgbase from the ROM
table; you need to specify it explicitly.");
return retval;
+ }
LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
coreidx, armv7a->debug_base);
} else
--
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