This is an automated email from Gerrit. Antony Pavlov ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2722
-- gerrit commit 17fd80fa82cedc09ff02e09f8bbb85f8a2965460 Author: Antony Pavlov <[email protected]> Date: Sat Apr 18 04:55:03 2015 +0300 WIP: tcl/board: add Black Swift board config TODOs: * ar9331_ddr2_init: add more comments; * move ar9331_25mhz_pll_init to common code; Change-Id: Iea3bd988c2ca773bc46c0014b2c0ee0a326d2c28 Signed-off-by: Antony Pavlov <[email protected]> diff --git a/tcl/board/black-swift.cfg b/tcl/board/black-swift.cfg new file mode 100644 index 0000000..1b67954 --- /dev/null +++ b/tcl/board/black-swift.cfg @@ -0,0 +1,52 @@ +source [find target/atheros_ar9331.cfg] + +# ar9331_25mhz_pll_init is imported from tcl/board/tp-link_tl-mr3020.cfg +proc ar9331_25mhz_pll_init {} { + mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4 + mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850) + mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL + ;# OUTDIV | REFDIV | DIV_INT + mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register + ;# (disabled?) + mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT + mww 0xb8050008 0x00008000 ;# remove bypass; + ;# AHB_POST_DIV - ratio 2 +} + +proc ar9331_ddr2_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb800008c 0x00000a59 + mww 0xb8000010 0x00000008 + mww 0xb8000090 0x00000000 + mww 0xb8000010 0x00000010 + mww 0xb8000094 0x00000000 + mww 0xb8000010 0x00000020 + mww 0xb800000c 0x00000000 + mww 0xb8000010 0x00000002 + mww 0xb8000008 0x00000100 + mww 0xb8000010 0x00000001 + mww 0xb8000010 0x00000008 + mww 0xb8000010 0x00000004 + mww 0xb8000010 0x00000004 + mww 0xb8000008 0x00000a33 + mww 0xb8000010 0x00000001 + mww 0xb800000c 0x00000382 + mww 0xb8000010 0x00000002 + mww 0xb800000c 0x00000402 + mww 0xb8000010 0x00000002 + mww 0xb8000014 0x00004186 + mww 0xb800001c 0x00000008 + mww 0xb8000020 0x00000009 + mww 0xb8000018 0x000000ff +} + +$TARGETNAME configure -event reset-init { + ar9331_25mhz_pll_init + sleep 1 + ar9331_ddr2_init +} + +set ram_boot_address 0xa0000000 +$TARGETNAME configure -work-area-phys 0xa1ffe000 -work-area-size 0x1000 -- ------------------------------------------------------------------------------ BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT Develop your own process in accordance with the BPMN 2 standard Learn Process modeling best practices with Bonita BPM through live exercises http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
