This is an automated email from Gerrit.
David Ung (dav...@nvidia.com) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/2744
-- gerrit
commit 5c3d18875b5c7bb6dfd46d4fbee3d0bd9548e4aa
Author: David Ung <dav...@nvidia.com>
Date: Thu Apr 23 13:22:13 2015 -0700
aarch64: Enable halting debug mode on breakpoint set
Ensure that we allow halting debug mode after setting breakpoint
Change-Id: I6f0d7a4a4775a93c133fb1ec31dfe3324d9f7395
Signed-off-by: David Ung <dav...@nvidia.com>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 772013b..34e6d52 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1258,6 +1258,7 @@ static int aarch64_set_breakpoint(struct target *target,
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
struct aarch64_brp *brp_list = aarch64->brp_list;
+ uint32_t dscr;
if (breakpoint->set) {
LOG_WARNING("breakpoint already set");
@@ -1322,6 +1323,17 @@ static int aarch64_set_breakpoint(struct target *target,
breakpoint->set = 0x11; /* Any nice value but 0 */
}
+ retval = mem_ap_sel_read_atomic_u32(armv8->arm.dap, armv8->debug_ap,
+ armv8->debug_base + CPUDBG_DSCR,
&dscr);
+ /* Ensure that halting debug mode is enable */
+ dscr = dscr | DSCR_HALT_DBG_MODE;
+ retval = mem_ap_sel_write_atomic_u32(armv8->arm.dap, armv8->debug_ap,
+ armv8->debug_base + CPUDBG_DSCR,
dscr);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("Failed to set DSCR.HDE");
+ return retval;
+ }
+
return ERROR_OK;
}
--
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