This is an automated email from Gerrit.

Matthias Welwarsky ([email protected]) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/3079

-- gerrit

commit 6493a245f0ba6bf9877f4f8fbd53df64b3a2e21c
Author: Matthias Welwarsky <[email protected]>
Date:   Thu Oct 29 13:09:29 2015 +0100

    cortex_a: force cache and tlb bypass when cpu is in debug state
    
    for minimal impact on the hardware state, force all memory accesses to
    bypass the caches and tlbs. This may actually be the default, but ARM
    recommends in DDI0406C to set proper default values on debug init.
    
    Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
    Signed-off-by: Matthias Welwarsky <[email protected]>

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index c96ef8f..a16f815 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -171,6 +171,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR           0x028
+#define CPUDBG_DSMCR           0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 84a13aa..48e5c61 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -243,6 +243,18 @@ static int cortex_a_init_debug_access(struct target 
*target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* Disable cacheline fills and force cache write-through in debug state 
*/
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+                       armv7a->debug_base + CPUDBG_DSCCR, 0);
+       if (retval != ERROR_OK)
+               return retval;
+
+       /* Disable TLB lookup and refill/eviction in debug state */
+       retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
+                       armv7a->debug_base + CPUDBG_DSMCR, 0);
+       if (retval != ERROR_OK)
+               return retval;
+
        /* Enabling of instruction execution in debug mode is done in 
debug_entry code */
 
        /* Resync breakpoint registers */

-- 

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