correction, mdw didn't worked on jetson even before (without 3165) > halt tegra124.cpu3 rev 3, partnum c0f, arch f, variant 3, implementor 41 tegra124.cpu3 cluster 0 core 3 multi core tegra124.cpu3: target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x60030093 pc: 0xc00395c8 MMU: enabled, D-Cache: enabled, I-Cache: enabled tegra124.cpu0 rev 3, partnum c0f, arch f, variant 3, implementor 41 tegra124.cpu0 cluster 0 core 0 multi core tegra124.cpu0: target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x60080093 pc: 0xc00395c8 MMU: enabled, D-Cache: enabled, I-Cache: enabled tegra124.cpu1 rev 3, partnum c0f, arch f, variant 3, implementor 41 tegra124.cpu1 cluster 0 core 1 multi core tegra124.cpu1: target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x60000093 pc: 0xc00395c8 MMU: enabled, D-Cache: enabled, I-Cache: enabled tegra124.cpu2 rev 3, partnum c0f, arch f, variant 3, implementor 41 tegra124.cpu2 cluster 0 core 2 multi core tegra124.cpu2: target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x600d0093 pc: 0xc00395c8 MMU: enabled, D-Cache: enabled, I-Cache: enabled > mdw 0x70830000 data abort at 0x70830000, dfsr = 0x00000206
and yes, they are running lpae enabled kernel. halted in supervisor mode. so it seems work as before On Fri, 11 Dec 2015 09:31:12 +0100, Matthias Welwarsky wrote: > On Thursday 10 December 2015 23:29:23 you wrote: >> hmm, on jetson (cortex a15) works halt/resume, but what doesn't work is mdw: >> > mdw 0x70832000 1024 >> >> data abort at 0x70832000, dfsr = 0x00000206 >> >> > dap info >> >> AP ID register 0x44770001 >> Type is MEM-AP AHB >> MEM-AP BASE 0xffffffff >> No ROM table present >> >> > mdw 0x70832000 1024 >> >> data abort at 0x70832000, dfsr = 0x00000206 > > Hum.. The DFSR is a bit strange. Bit[9] hints that the OS is using the "long" > descriptor format for page tables. LPAE enabled? Also, the status bits decode > to "000110", which is a MMU translation fault, at level 2! Is there a > hypervisor active? I would not be surprised, knowing that it's a Qualcomm > device. If yes, you can assume that you tried to access a memory region that > has not been mapped into your VM. In which mode did you halt the cores? > > BR, > Matthias > > > ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
