Why is the SSTICKYERR bit in DP_CTRL_STAT being set to 1 in the dap_dp_init() routine in arm_adi_v5.c?
This is causing a SWD FAULT with WDATAERR=1 on my LPC11U68 chip. Commenting out the SSTICKYERR set clears this problem up for me, and I can't understand why this flag was being set in the first place in the DP init code. The ADIv5 spec (IHI 0031C, Issue C, p .48) says this is RO/WI bit for a SW-DP and R/W1C for a JTAG-DP. Looking in the Glossary: For SW-DP: RO: Read only WI: Writes ignored FOR JTAG-DP: W1C: Writing a 1 to the bit clears the bit to 0. Writing a 0 to the bit has no effect. So it must be that the intention is to *clear* SSTICKYERR instead of setting it to 1, due to the JTAG-DP W1C definition. But that doesn't work for the SW-DP. Instead, the spec says, in order to clear this flag (p. 51): "To clear STICKYERR to 0, write 1 to the ABORT.STKERRCLR field." For SW-DP, writing a 1 is supposed to be ignored (WI), but on a LPC11U68 that doesn't seem to be the case. It results in a WDATAERR FAULT. I can work on a patch to do things differently in dap_dp_init() in JTAG mode vs SWD mode, but I wanted to check first to see if setting SSTICKYERR=1 serves some kind of purpose in SWD mode that I am not realizing.
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