Thank you, the stm32f2x.c source file looks really comprehensive, a more
detailed stm32lx_probe() function would for the STM32LX...
I don't know much about **option bytes** yet.
What are doing exactly with the (user) option bytes there?
---
Looking into those functions in stm32f2x.c:
stm32x_unlock_option_reg()
stm32x_read_options()
stm32x_write_options()
Also:
stm32x_probe()
stm32x_auto_probe()
get_stm32x_info()
...
---
And trying to figure out some things with the STM32L0x2 reference manual
(RM0376, http://st.com/resource/en/reference_manual/DM00108281.pdf)
3 Flash program memory and data EEPROM (FLASH)
3.3.1 NVM organization, Table 5. NVM organization:
0x1FF80000 - 0x1FF8001F 32 bytes User Option bytes
3.7.6 Option bytes unlock key register (FLASH_OPTKEYR)
Address offset: 0x14
-> Address: 0x40022014
3.7.8 Option bytes register (FLASH_OPTR)
Address offset 0x1C
-> Address: 0x4002201C
During production, it is set to 0x8070 00AA.
> check in OpenOCD: stm32l0.cpu mdw 0x4002201C
0x4002201c 807000aa
3.7.11 Flash register map
...
3.8 Option bytes
On the NVM, an area is reserved to store a set of Option bytes which are used
to configure the product. Some option bytes are written in factory while others
can be configured by the end user.
The configuration managed by an end user is stored the Option bytes area
(32 bytes).
(...)
The Option bytes are automatically loaded during the boot. They are used to set
the content of the FLASH_OPTR and FLASH_WRPROTx registers.
The Option bytes can be read from the memory locations listed:
~~~
0x1FF80000 FLASH_OPTR[15:0]
0x1FF80004 FLASH_OPTR[31:16]
0x1FF80008 FLASH_WRPROT1[15:0]
0x1FF8000C FLASH_WRPROT1[31:16]
0x1FF80010 FLASH_WRPROT2[15:0]
~~~
Hmm...
---
Verifying some addresses and offsets in stm32l072xx.h:
~~~
/*!< Peripheral base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000U)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
/*!< FLASH registers base address */
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
~~~
-> Flash register base address: 0x40022000
~~~
/*!< FLASH Option Bytes base address */
#define OB_BASE ((uint32_t)0x1FF80000U)
/*!< FLASH Size register base address */
#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU)
/*!< Unique device ID register base address */
#define UID_BASE ((uint32_t)0x1FF80050U)
~~~
*just some notes*
---
** [tickets:#148] STM32L0x: flash size and dual bank support**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Sun Mar 19, 2017 09:20 AM UTC
**Owner:** nobody
Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.
Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program
build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is
0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~
Then I've realized that there are two flash program memory banks:
STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB
So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~
But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program
build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is
0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should
rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~
So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~
That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c
"program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is
0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is
0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~
So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/
But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...
See also:
http://openocd.zylin.com/#/c/3554/
STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf
I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...
-----
Possible solutions that came to mind:
1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on
STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).
2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.
3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?
I'd like to help fixing this issue...
---
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