> Hi Cezary, thanks for the summary of the memory layouts, this is what I
> planned to look into as well :)
>
> At the moment I'm trying out your patch: http://openocd.zylin.com/#/c/4074/
>
> http://openocd.zylin.com/#/c/4074/2/src/flash/nor/stm32lx.c
>
> It looks like a nice solution and works for my STM32L082 board! (Are really
> all variants covered?)
I hope so, that it should works for all listed devices if the reference manuals
from ST are correct and I didn't have make any mistake :).
> But what about the the L0s that don't have two flash banks? Is it up to the
> user to decide whether to use stm32l0.cfg or stm32l0x_dual_bank.cfg ? - The
> latter would only be needed for large binaries, otherwise the stm32l0.cfg
> would work fine?
I think that always correct cfg file should be used for the MCU. If device has
two banks that stm32l0x_dual_bank.cfg also should be used without any
dependency of binaries size. Please notice that dual bank can be used also when
binaries are smaller but someone need to boot up device from second bank like
for example in 3.3.2 Dual-bank boot capability (RM0377).
> Jan Čapek also worked on a solution for the same problem:
> http://openocd.zylin.com/#/c/4076/2
I know and I noticed that is not fully solve the problem (with links to yours
and my patch). You can also write a post for his change and that you have tried
to solve this problem earlier.
> Correction: Not sure if it needs a special CFG file, since the patch actually
> already figures out if the MCU has a dual bank layout...
>
> It detects the device and first bank correctly:
>
> Info : Device: STM32L0xx (Cat.5)
> Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is
> 0x8000000
>
> But then fails writing beyond 0x08018000 (second bank)...
>
> Warn : no flash bank found for address 8018000
> Warn : no flash bank found for address 8025ff4
>
> Here, a full print out (with usual warnings, and actual errors)..
>
> $ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg
> -c "program build/prj.elf verify reset exit" --search ~/git/openocd/tcl
> Open On-Chip Debugger 0.10.0+dev-00094-gfc738c70 (2017-03-21-11:32)
> Licensed under GNU GPL v2
> For bug reports, read
> http://openocd.org/doc/doxygen/bugs.html
> Info : auto-selecting first available session transport "hla_swd". To
> override use 'transport select <transport>'.
> adapter speed: 300 kHz
> adapter_nsrst_delay: 100
> Info : The selected transport took over low-level target control. The results
> might differ compared to plain JTAG/SWD
> none separate
> Info : Unable to match requested speed 300 kHz, using 240 kHz
> Info : Unable to match requested speed 300 kHz, using 240 kHz
> Info : clock speed 240 kHz
> Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748
> Info : using stlink api v2
> Info : Target voltage: 3.485039
> Info : stm32l0.cpu: hardware has 4 breakpoints, 2 watchpoints
> adapter speed: 300 kHz
> target halted due to debug-request, current mode: Thread
> xPSR: 0xf1000000 pc: 0x08018e14 msp: 0x20005000
> STM32L0: Enabling HSI16
> adapter speed: 2500 kHz
> ** Programming Started **
> auto erase enabled
> Info : Device: STM32L0xx (Cat.5)
> Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is
> 0x8000000
> Warn : couldn't use loader, falling back to page memory writes
> Warn : no flash bank found for address 8018000
> Warn : no flash bank found for address 8025ff4
> wrote 98304 bytes from file build/prj.elf in 37.422348s (2.565 KiB/s)
> ** Programming Finished **
> ** Verify Started **
> Error: JTAG failure
> Error: Error setting register
> target halted due to breakpoint, current mode: Handler HardFault
> xPSR: 0x61000003 pc: 0x2000002e msp: 0x20005000
> Error: JTAG failure
> Error: Error setting register
> target halted due to breakpoint, current mode: Handler HardFault
> xPSR: 0x61000003 pc: 0x2000002e msp: 0x20005000
> verified 156464 bytes in 0.970004s (157.522 KiB/s)
> ** Verified OK **
> ** Resetting Target **
> adapter speed: 300 kHz
> shutdown command invoked
Hmm, I'm not sure but for me that works correctly. Can you show the stm32l0.cfg
file?
> Cezary, you've also added a dual bank config file there:
> http://openocd.zylin.com/#/c/3554/3/tcl/target/stm32l0_192KB_dual_bank.cfg
>
> # The stm32l0 192 Kbyte category 5 devices dual bank flash.
> # Overwritting a definition for the first and add second bank here.
>
> set FLASHSIZE 98304
>
> source [find target/stm32l0.cfg]
>
> # Add the second flash bank.
> set _FLASHNAME $_CHIPNAME.flash1
> flash bank $_FLASHNAME stm32lx 0 $FLASHSIZE 0 0 $_TARGETNAME
>
> Would it necessary to specify the size? Wouldn't 0 let OpenOCD determine the
> size by your new patch?
For the first glance this file works for me and I don't have any warnings.
Please notice that this patch (http://openocd.zylin.com/#/c/3554) is canceled
because of new patch.
Jan Čapek created good config files for NUCLEO-L073RZ here:
http://openocd.zylin.com/#/c/3957/ and here the flash memory size is leaved to
zero value.
BTW, you are using STM32L082 on custom board or this is some sort of evaluation
board. If it's eval board perhaps you can create a patch with yout board
configuration?
---
** [tickets:#148] STM32L0x: flash size and dual bank support**
**Status:** new
**Milestone:** 0.9.0
**Created:** Sun Mar 19, 2017 01:47 AM UTC by Aurelio Lucchesi
**Last Updated:** Tue Mar 21, 2017 11:18 AM UTC
**Owner:** nobody
Flash programming large binaries to my STM32L082 board failed,
and I had to recompile OpenOCD in order to make it work.
Without modification, it looks like this:
~~~
$ openocd -f interface/stlink-v2.cfg -f target/stm32l0.cfg -c "program
build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is
0x8000000
...
Error: checksum mismatch - attempting binary compare
diff 0 address 0x08020000. Was 0x3e instead of 0x69
diff 1 address 0x08020001. Was 0x79 instead of 0x21
diff 2 address 0x08020002. Was 0x79 instead of 0x3d
diff 3 address 0x08020003. Was 0x74 instead of 0x59
diff 4 address 0x08020004. Was 0x6f instead of 0x59
diff 5 address 0x08020005. Was 0x73 instead of 0x5f
...
~~~
Then I've realized that there are two flash program memory banks:
STM32L0xx category 5 MCUs come with 192 KiB of Flash program memory:
* Bank 1: starting at 0x0800 0000, size 96 KiB
* Bank 2: starting at 0x0801 8000, size 96 KiB
So I've added a second one to a copy of the stm32l0.cfg script:
~~~
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
# add second flash bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x08018000 0x18000 0 0 $_TARGETNAME
~~~
But that revealed another problem:
~~~
$ openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c "program
build/prj.elf reset exit verify"
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 128kb, base address is
0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Warn : STM32L flash bank base address config is incorrect. 0x8018000 but should
rather be 0x8000000 or 0x8020000
Error: auto_probe failed
** Programming Failed **
shutdown command invoked
~~~
So I tried to fix things by rebuilding OpenOCD, and changed the size of
the first (and second) flash page in src/flash/nor/stm32lx.c:261 from
128 to 96 KiB:
~~~
{
.id = 0x447,
.revs = stm32_447_revs,
.num_revs = ARRAY_SIZE(stm32_447_revs),
.device_str = "STM32L0xx (Cat.5)",
.page_size = 128,
.pages_per_sector = 32,
.max_flash_size_kb = 192,
.first_bank_size_kb = 96, // 128,
.has_dual_banks = true,
.flash_base = 0x40022000,
.fsize_base = 0x1FF8007C,
},
~~~
That actually works for my hardware with the modified cfg script:
~~~
$ ~/git/openocd/src/openocd -f interface/stlink-v2.cfg -f ./stm32l0.cfg -c
"program build/prj.elf reset exit verify" --search
~/git/openocd/tcl
Open On-Chip Debugger 0.10.0+dev-00093-g6b2acc02 (2017-03-18-23:04)
...
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is
0x8000000
Warn : couldn't use loader, falling back to page memory writes
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is
0x8018000
Info : ignoring flash probed value, using configured bank size: 96kbytes
...
** Verified OK **
** Resetting Target **
~~~
So I've asked on IRC and tried to submit a really simple patch for that:
http://openocd.zylin.com/#/c/4073/
But like Cezary pointed out: This **does not solve the problem of all STM32L0**
Category 5 (or 3) devices, since they all have a different memory layout...
See also:
http://openocd.zylin.com/#/c/3554/
STM32L0x1 Ref Manual: http://st.com/resource/en/reference_manual/DM00108282.pdf
STM32L0x2 Ref Manual: http://st.com/resource/en/reference_manual/DM00108281.pdf
STM32L0x3 Ref Manual: http://st.com/resource/en/reference_manual/DM00095744.pdf
I don't have access to other hardware to test things out nor enough knowledge
about OpenOCD to really fix the issue for all cases...
-----
Possible solutions that came to mind:
1) Don't use hardcoded size values. - Like Karl Palsson pointed out:
Using the probed flash size (fsize_base/flash_size_in_kb, 0x1FF8004C on
STM32L0x2,
33.1.1 Flash size register) and the device ID (32.4.1 MCU device ID code,
stm32lx_read_id_code()), it should be possible to figure out the exact flash
memory layout (size, addresses, dual bank).
2) Hardcode the values for all possible combinations for all STM32L0 MCU
types/categories code the sizes.
3) Maybe the easiest: Make it possible to change first_bank_size_kb in a
config script? Or is this already possible somehow?
I'd like to help fixing this issue...
---
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