Hi,

in the past several people have tried to use OpenOCD to debug JZ47xx
processors, but have failed because OpenOCD was unable to reset the
ROCC bit in the ECR ([1], [2]). There are two issues with the EJTAG
implementation in the JZ47xx that cause this:

1. ROCC is R/W instead of R/W0 on this processor. The easiest way
   to work around this is to remove EJTAG_CTRL_ROCC from
   ejtag_info->ejtag_ctrl.

2. Pause-DR while the ECR is selected is equal to the Capture-DR
   state. So probes/drivers that always pass through Pause-DR on their
   way from Shift-DR to Update-DR (f.ex. the USB Blaster driver) will
   discard the value that has been shifted in before the ECR is updated.

Working around these two problems makes OpenOCD start up. But there
is a third implementation detail that needs a workaround:

The XBurst Branch Target Buffer may be enabled and it will remember
when there was an unconditional branch in drseg. We need to disable
it by setting bit 0 in CP0's config7 register. If the BTB stays
enabled, the code snippets executed from drseg will jump back to
0xff200200 even if the instruction fetched is no branch instruction,
just because there was one at that address in a previous snippet.
I put the instrucions to change config7 into mips32_pracc_read_regs
and am now able to halt and single-step the cpu.

For JZ4730 there exists no public documentation for config7 apart from
the Ingenic JDI manual, where it is said that writing 1 to that register
"closes" the BTB optimization of the JZ4730. For the JZ4750 there is a
two-page document describing the performance monitor (PMon) that is also
configured in config7. According to that document, there is also bit 1
to invalidate the BTB. The U-Boot code release by Ingenic for the JZ4730
sets bit 1 in flush_icache_all.

So, where are the correct places to add the ROCC and BTB workarounds?

Best regards,

  Daniel


[1] https://sourceforge.net/p/openocd/mailman/message/32872860/
[2] https://groups.google.com/forum/#!topic/mips-creator-ci20/yEYqrx2L8mA

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