This is an automated email from Gerrit.
Tim Newsome (t...@sifive.com) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/4655
-- gerrit
commit 227ef26843b643be63d0da510e64a269654f4d17
Author: Tim Newsome <t...@sifive.com>
Date: Fri Aug 24 13:01:49 2018 -0700
Clarify what exactly the RISC-V code supports.
Change-Id: I8da657426cc52c738ab41bfb0164cbc6721c0aef
Signed-off-by: Tim Newsome <t...@sifive.com>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c0d065d..5fbd082 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8974,8 +8974,11 @@ Display all registers in @emph{group}.
@section RISC-V Architecture
@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
-debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug
-Specification.
+debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
+harts. (It's possible to increase this limit to 1024 by changing
+RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
+Debug Specification, but there is also support for legacy targets that
+implement version 0.11.
@subsection RISC-V Terminology
--
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