This is an automated email from Gerrit. Kevin Gillespie ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4750
-- gerrit commit 0f4b07386bcb3facbc6d788df8f35332e11c5ec9 Author: Kevin Gillespie <[email protected]> Date: Mon Sep 24 16:21:22 2018 -0500 max32xxx: Cleanup, 128-bit flash, new targets. Removing unused variable and buffer manipulation in get_info function. Recompiling assembly files to get propper data into write_code. Adding support for 128-bit flash operations. Adding configuration files for new targets. Moving common configuration into shared file. Change-Id: I043e861f958c6926a46735f23f6b6b466edf2a92 Signed-off-by: Kevin Gillespie <[email protected]> diff --git a/contrib/loaders/flash/max32xxx/max32xxx.inc b/contrib/loaders/flash/max32xxx/max32xxx.inc index 442165d..826dc44 100644 --- a/contrib/loaders/flash/max32xxx/max32xxx.inc +++ b/contrib/loaders/flash/max32xxx/max32xxx.inc @@ -1,6 +1,15 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ -0xdf,0xf8,0x44,0x40,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x1a,0xd0,0x47,0x68, -0x47,0x45,0xf7,0xd0,0x22,0x60,0x02,0xf1,0x04,0x02,0x57,0xf8,0x04,0x8b,0xc4,0xf8, -0x30,0x80,0xa5,0x68,0x45,0xf0,0x01,0x05,0xa5,0x60,0xd4,0xf8,0x08,0x80,0x18,0xf0, -0x01,0x0f,0xfa,0xd1,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x01,0x3b, -0x03,0xb1,0xdf,0xe7,0x00,0xbe,0x00,0xbf,0x00,0x00,0x00,0x40, +0xa6,0x68,0x46,0xf0,0x10,0x06,0xa6,0x60,0x15,0xf0,0x01,0x0f,0x03,0xd0,0xa6,0x68, +0x26,0xf0,0x10,0x06,0xa6,0x60,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x55,0xd0, +0x47,0x68,0x47,0x45,0xf7,0xd0,0x22,0x60,0x02,0xf1,0x04,0x02,0x15,0xf0,0x01,0x0f, +0x01,0xd0,0x02,0xf1,0x0c,0x02,0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x30,0x80,0x8f,0x42, +0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x15,0xf0,0x01,0x0f,0x32,0xd0,0xd0,0xf8, +0x00,0x80,0xb8,0xf1,0x00,0x0f,0x39,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0,0x57,0xf8, +0x04,0x8b,0xc4,0xf8,0x34,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60, +0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x28,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0, +0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x38,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07, +0x47,0x60,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x17,0xd0,0x47,0x68,0x47,0x45, +0xf7,0xd0,0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x3c,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1, +0x08,0x07,0x47,0x60,0xa6,0x68,0x46,0xf0,0x01,0x06,0xa6,0x60,0xd4,0xf8,0x08,0x80, +0x18,0xf0,0x07,0x0f,0xfa,0xd1,0x01,0x3b,0x03,0xb1,0xa4,0xe7,0xa6,0x68,0x46,0xf0, +0x10,0x06,0xa6,0x60,0x00,0xbe, diff --git a/contrib/loaders/flash/max32xxx/max32xxx.s b/contrib/loaders/flash/max32xxx/max32xxx.s index f5306d6..9dcede9 100644 --- a/contrib/loaders/flash/max32xxx/max32xxx.s +++ b/contrib/loaders/flash/max32xxx/max32xxx.s @@ -27,44 +27,120 @@ * r0 = workarea start * r1 = workarea end * r2 = target address - * r3 = count (32bit words) + * r3 = count (number of writes) * r4 = pFLASH_CTRL_BASE - * + * r5 = 128-bit write + * Clobbered: - * r5 = FLASHWRITECMD + * r6 = FLASHWRITECMD * r7 - rp * r8 - wp, tmp */ write: + /* write in 32-bit units by default */ + ldr r6, [r4, #0x08] /* FLSH_CN */ + orr r6, r6, #0x10 /* Width 32 bits */ + str r6, [r4, #0x08] /* FLSH_CN */ + + tst r5, #1 /* Check 32-bit write options */ + beq wait_fifo + + /* Enable 128-bit write */ + ldr r6, [r4, #0x08] /* FLSH_CN */ + bic r6, r6, #0x10 /* Width 128 bits */ + str r6, [r4, #0x08] /* FLSH_CN */ + wait_fifo: -ldr r8, [r0, #0] /* read wp */ -cmp r8, #0 /* abort if wp == 0 */ -beq exit -ldr r7, [r0, #4] /* read rp */ -cmp r7, r8 /* wait until rp != wp */ -beq wait_fifo + ldr r8, [r0, #0x00] /* read wp */ + cmp r8, #0x00 /* abort if wp == 0 */ + beq exit + ldr r7, [r0, #0x04] /* read rp */ + cmp r7, r8 /* wait until rp != wp */ + beq wait_fifo mainloop: -str r2, [r4, #0x00] /* FLSH_ADDR - write address */ -add r2, r2, #4 /* increment target address */ -ldr r8, [r7], #4 -str r8, [r4, #0x30] /* FLSH_DATA0 - write data */ -ldr r5, [r4, #0x08] /* FLSH_CN */ -orr r5, r5, #1 -str r5, [r4, #0x08] /* FLSH_CN - enable write */ + + str r2, [r4, #0x00] /* FLSH_ADDR - write address */ + add r2, r2, #0x04 /* increment target address */ + tst r5, #1 /* Check 32-bit write options */ + beq inc32 + add r2, r2, #0x0C /* additional 12 if 128-bit write*/ + +inc32: + ldr r8, [r7], #0x04 + str r8, [r4, #0x30] /* FLSH_DATA0 - write data */ + cmp r7, r1 /* wrap rp at end of buffer */ + it cs + addcs r7, r0, #0x08 /* skip loader args */ + str r7, [r0, #0x04] /* store rp */ + + tst r5, #1 /* Check 32-bit write options */ + beq write32 + +wait_fifo0: + ldr r8, [r0, #0x00] /* read wp */ + cmp r8, #0x00 /* abort if wp == 0 */ + beq exit + ldr r7, [r0, #0x04] /* read rp */ + cmp r7, r8 /* wait until rp != wp */ + beq wait_fifo0 + + ldr r8, [r7], #0x04 + str r8, [r4, #0x34] /* FLSH_DATA1 - write data */ + cmp r7, r1 /* wrap rp at end of buffer */ + it cs + addcs r7, r0, #0x08 /* skip loader args */ + str r7, [r0, #0x04] /* store rp */ + +wait_fifo1: + ldr r8, [r0, #0x00] /* read wp */ + cmp r8, #0x00 /* abort if wp == 0 */ + beq exit + ldr r7, [r0, #0x04] /* read rp */ + cmp r7, r8 /* wait until rp != wp */ + beq wait_fifo1 + + ldr r8, [r7], #0x04 + str r8, [r4, #0x38] /* FLSH_DATA2 - write data */ + cmp r7, r1 /* wrap rp at end of buffer */ + it cs + addcs r7, r0, #0x08 /* skip loader args */ + str r7, [r0, #0x04] /* store rp */ + +wait_fifo2: + ldr r8, [r0, #0x00] /* read wp */ + cmp r8, #0x00 /* abort if wp == 0 */ + beq exit + ldr r7, [r0, #0x04] /* read rp */ + cmp r7, r8 /* wait until rp != wp */ + beq wait_fifo2 + + ldr r8, [r7], #0x04 + str r8, [r4, #0x3C] /* FLSH_DATA3 - write data */ + cmp r7, r1 /* wrap rp at end of buffer */ + it cs + addcs r7, r0, #0x08 /* skip loader args */ + str r7, [r0, #0x04] /* store rp */ + +write32: + ldr r6, [r4, #0x08] /* FLSH_CN */ + orr r6, r6, #0x01 /* WE */ + str r6, [r4, #0x08] /* FLSH_CN - enable write */ + busy: -ldr r8, [r4, #0x08] /* FLSH_CN */ -tst r8, #1 -bne busy - -cmp r7, r1 /* wrap rp at end of buffer */ -it cs -addcs r7, r0, #8 /* skip loader args */ -str r7, [r0, #4] /* store rp */ -subs r3, r3, #1 /* decrement word count */ -cbz r3, exit /* loop if not done */ -b wait_fifo + ldr r8, [r4, #0x08] /* FLSH_CN */ + tst r8, #0x07 + bne busy + + subs r3, r3, #0x01 /* decrement write count */ + cbz r3, exit /* loop if not done */ + b wait_fifo + exit: -bkpt + /* restore flash settings */ + ldr r6, [r4, #0x08] /* FLSH_CN */ + orr r6, r6, #0x10 /* Width 32 bits */ + str r6, [r4, #0x08] /* FLSH_CN */ + bkpt diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c index ca037de..8217eea 100644 --- a/src/flash/nor/max32xxx.c +++ b/src/flash/nor/max32xxx.c @@ -24,48 +24,71 @@ #include <target/algorithm.h> #include <target/armv7m.h> -/* Register Addresses */ -#define FLSH_ADDR 0x000 -#define FLSH_CLKDIV 0x004 -#define FLSH_CN 0x008 -#define PR1E_ADDR 0x00C -#define PR2S_ADDR 0x010 -#define PR2E_ADDR 0x014 -#define PR3S_ADDR 0x018 -#define PR3E_ADDR 0x01C -#define FLSH_MD 0x020 -#define FLSH_INT 0x024 -#define FLSH_DATA0 0x030 -#define FLSH_DATA1 0x034 -#define FLSH_DATA2 0x038 -#define FLSH_DATA3 0x03C -#define FLSH_BL_CTRL 0x170 -#define FLSH_PROT 0x300 - -#define ARM_PID_REG 0xE00FFFE0 -#define MAX326XX_ID_REG 0x40000838 +/* Register addresses */ +#define FLC_ADDR 0x00000000 +#define FLC_CLKDIV 0x00000004 +#define FLC_CN 0x00000008 +#define FLC_PR1E_ADDR 0x0000000C +#define FLC_PR2S_ADDR 0x00000010 +#define FLC_PR2E_ADDR 0x00000014 +#define FLC_PR3S_ADDR 0x00000018 +#define FLC_PR3E_ADDR 0x0000001C +#define FLC_MD 0x00000020 +#define FLC_INT 0x00000024 +#define FLC_DATA0 0x00000030 +#define FLC_DATA1 0x00000034 +#define FLC_DATA2 0x00000038 +#define FLC_DATA3 0x0000003C +#define FLC_BL_CTRL 0x00000170 +#define FLC_PROT 0x00000300 + +#define ARM_PID_REG 0xE00FFFE0 +#define MAX326XX_ID_REG 0x40000838 /* Register settings */ -#define FLSH_INT_AF 0x00000002 - -#define FLSH_CN_UNLOCK_MASK 0xF0000000 -#define FLSH_CN_UNLOCK_VALUE 0x20000000 - -#define FLSH_CN_PEND 0x01000000 - -#define FLSH_CN_ERASE_CODE_MASK 0x0000FF00 -#define FLSH_CN_ERASE_CODE_PGE 0x00005500 -#define FLSH_CN_ERASE_CODE_ME 0x0000AA00 - -#define FLSH_CN_PGE 0x00000004 -#define FLSH_CN_ME 0x00000002 -#define FLSH_CN_WR 0x00000001 -#define FLASH_BL_CTRL_23 0x00020000 -#define FLASH_BL_CTRL_IFREN 0x00000001 - -#define ARM_PID_DEFAULT_CM3 0xB4C3 -#define ARM_PID_DEFAULT_CM4 0xB4C4 -#define MAX326XX_ID 0x4D +#define FLC_INT_AF 0x00000002 + +#define FLC_CN_UNLOCK_MASK 0xF0000000 +#define FLC_CN_UNLOCK_VALUE 0x20000000 + +#define FLC_CN_PEND 0x01000000 +#define FLC_CN_ERASE_CODE_MASK 0x0000FF00 +#define FLC_CN_ERASE_CODE_PGE 0x00005500 +#define FLC_CN_ERASE_CODE_ME 0x0000AA00 +#define FLC_CN_32BIT 0x00000010 +#define FLC_CN_PGE 0x00000004 +#define FLC_CN_ME 0x00000002 +#define FLC_CN_WR 0x00000001 +#define FLC_CN_PGE 0x00000004 +#define FLC_CN_ME 0x00000002 +#define FLC_CN_WR 0x00000001 + +#define FLC_BL_CTRL_23 0x00020000 +#define FLC_BL_CTRL_IFREN 0x00000001 + +#define MASK_FLASH_BUSY (0x048800E0 & ~0x04000000) +#define MASK_DISABLE_INTS (0xFFFFFCFC) +#define MASK_FLASH_UNLOCKED (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_LOCK (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_ERASE (0xF588FFEF & ~0x04000000) +#define MASK_FLASH_ERASED (0xF48800EB & ~0x04000000) +#define MASK_ACCESS_VIOLATIONS (0xFFFFFCFC) +#define MASK_FLASH_WRITE (0xF588FFEF & ~0x04000000) +#define MASK_WRITE_ALIGNED (0xF588FFEF & ~0x04000000) +#define MASK_WRITE_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_WRITE_BURST (0xF588FFEF & ~0x04000000) +#define MASK_BURST_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_WRITE_REMAINING (0xF588FFEF & ~0x04000000) +#define MASK_REMAINING_COMPLETE (0xF488FFEE & ~0x04000000) +#define MASK_MASS_ERASE (0xF588FFEF & ~0x04000000) +#define MASK_ERASE_COMPLETE (0xF48800ED & ~0x04000000) + +#define ARM_PID_DEFAULT_CM3 0x0000B4C3 +#define ARM_PID_DEFAULT_CM4 0x0000B4C4 +#define MAX326XX_ID 0x0000004D + +#define WRITE32BIT 0 +#define WRITE128BIT 1 static int max32xxx_mass_erase(struct flash_bank *bank); @@ -85,7 +108,7 @@ static const uint8_t write_code[] = { #include "../../contrib/loaders/flash/max32xxx/max32xxx.inc" }; -/* Config Command: flash bank name driver base size chip_width bus_width target [driver_option] +/* Config Command: flash bank name driver base size chip_width bus_width target [driver_option] flash bank max32xxx <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits] */ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) @@ -93,7 +116,10 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) struct max32xxx_flash_bank *info; if (CMD_ARGC < 9) { - LOG_WARNING("incomplete flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]"); + LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]"); + return ERROR_FLASH_BANK_INVALID; + } else if (CMD_ARGC > 10) { + LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]"); return ERROR_FLASH_BANK_INVALID; } @@ -103,10 +129,17 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->sector_size); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], info->clkdiv_value); - if (CMD_ARGC > 9) + if (CMD_ARGC == 10) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->burst_size_bits); - else + else { + /* Default burst size of 32 bits */ info->burst_size_bits = 32; + } + + if ((info->burst_size_bits != 128) && (info->burst_size_bits != 32)) { + LOG_ERROR("Invalid burst size %d, must be 32 or 128", info->burst_size_bits); + return ERROR_FLASH_BANK_INVALID; + } info->int_state = 0; bank->driver_priv = info; @@ -115,75 +148,73 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command) static int get_info(struct flash_bank *bank, char *buf, int buf_size) { - int printed; struct max32xxx_flash_bank *info = bank->driver_priv; if (info->probed == 0) return ERROR_FLASH_BANK_NOT_PROBED; - printed = snprintf(buf, buf_size, "\nMaxim Integrated max32xxx flash driver\n"); - buf += printed; - buf_size -= printed; + snprintf(buf, buf_size, "\nMaxim Integrated max32xxx flash driver\n"); return ERROR_OK; } -/*************************************************************************** -* flash operations -***************************************************************************/ +static int max32xxx_flash_busy(uint32_t flash_cn) +{ + if (flash_cn & (FLC_CN_PGE | FLC_CN_ME | FLC_CN_WR)) + return ERROR_FLASH_BUSY; + + return ERROR_OK; +} static int max32xxx_flash_op_pre(struct flash_bank *bank) { struct target *target = bank->target; struct max32xxx_flash_bank *info = bank->driver_priv; - uint32_t flsh_cn; + uint32_t flash_cn; uint32_t bootloader; /* Check if the flash controller is busy */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - if (flsh_cn & (FLSH_CN_PEND | FLSH_CN_ERASE_CODE_MASK | FLSH_CN_PGE | - FLSH_CN_ME | FLSH_CN_WR)) + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + if (max32xxx_flash_busy(flash_cn)) return ERROR_FLASH_BUSY; /* Refresh flash controller timing */ - target_write_u32(target, info->flc_base + FLSH_CLKDIV, info->clkdiv_value); + target_write_u32(target, info->flc_base + FLC_CLKDIV, info->clkdiv_value); /* Clear and disable flash programming interrupts */ - target_read_u32(target, info->flc_base + FLSH_INT, &info->int_state); - target_write_u32(target, info->flc_base + FLSH_INT, 0x00000000); + target_read_u32(target, info->flc_base + FLC_INT, &info->int_state); + target_write_u32(target, info->flc_base + FLC_INT, 0); /* Clear the lower bit in the bootloader configuration register in case flash page 0 has been replaced */ - if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) { - LOG_ERROR("Read failure on FLSH_BL_CTRL"); + if (target_read_u32(target, info->flc_base + FLC_BL_CTRL, &bootloader) != ERROR_OK) { + LOG_ERROR("Read failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (bootloader & FLASH_BL_CTRL_23) { - LOG_WARNING("FLSH_BL_CTRL indicates BL mode 2 or mode 3."); - if (bootloader & FLASH_BL_CTRL_IFREN) { + if (bootloader & FLC_BL_CTRL_23) { + LOG_WARNING("FLC_BL_CTRL indicates BL mode 2 or mode 3."); + if (bootloader & FLC_BL_CTRL_IFREN) { LOG_WARNING("Flash page 0 swapped out, attempting to swap back in for programming"); - bootloader &= ~(FLASH_BL_CTRL_IFREN); - if (target_write_u32(target, info->flc_base + FLSH_BL_CTRL, bootloader) != ERROR_OK) { - LOG_ERROR("Write failure on FLSH_BL_CTRL"); + bootloader &= ~(FLC_BL_CTRL_IFREN); + if (target_write_u32(target, info->flc_base + FLC_BL_CTRL, bootloader) != ERROR_OK) { + LOG_ERROR("Write failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (target_read_u32(target, info->flc_base + FLSH_BL_CTRL, &bootloader) != ERROR_OK) { - LOG_ERROR("Read failure on FLSH_BL_CTRL"); + if (target_read_u32(target, info->flc_base + FLC_BL_CTRL, &bootloader) != ERROR_OK) { + LOG_ERROR("Read failure on FLC_BL_CTRL"); return ERROR_FAIL; } - if (bootloader & FLASH_BL_CTRL_IFREN) { - /* Bummer */ + if (bootloader & FLC_BL_CTRL_IFREN) LOG_ERROR("Unable to swap flash page 0 back in. Writes to page 0 will fail."); - } } } /* Unlock flash */ - flsh_cn &= ~FLSH_CN_UNLOCK_MASK; - flsh_cn |= FLSH_CN_UNLOCK_VALUE; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + flash_cn &= ~(FLC_CN_UNLOCK_MASK); + flash_cn |= FLC_CN_UNLOCK_VALUE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Confirm flash is unlocked */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - if ((flsh_cn & FLSH_CN_UNLOCK_VALUE) != FLSH_CN_UNLOCK_VALUE) + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + if ((flash_cn & FLC_CN_UNLOCK_VALUE) != FLC_CN_UNLOCK_VALUE) return ERROR_FAIL; return ERROR_OK; @@ -193,15 +224,15 @@ static int max32xxx_flash_op_post(struct flash_bank *bank) { struct target *target = bank->target; struct max32xxx_flash_bank *info = bank->driver_priv; - uint32_t flsh_cn; + uint32_t flash_cn; /* Restore flash programming interrupts */ - target_write_u32(target, info->flc_base + FLSH_INT, info->int_state); + target_write_u32(target, info->flc_base + FLC_INT, info->int_state); /* Lock flash */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= ~FLSH_CN_UNLOCK_MASK; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn &= ~(FLC_CN_UNLOCK_MASK); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); return ERROR_OK; } @@ -225,7 +256,7 @@ static int max32xxx_protect_check(struct flash_bank *bank) /* Check the protection */ for (i = 0; i < bank->num_sectors; i++) { if (i%32 == 0) - target_read_u32(target, info->flc_base + FLSH_PROT + ((i/32)*4), &temp_reg); + target_read_u32(target, info->flc_base + FLC_PROT + ((i/32)*4), &temp_reg); if (temp_reg & (0x1 << i%32)) bank->sectors[i].is_protected = 1; @@ -238,7 +269,7 @@ static int max32xxx_protect_check(struct flash_bank *bank) static int max32xxx_erase(struct flash_bank *bank, int first, int last) { int banknr; - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; int retval; @@ -275,22 +306,22 @@ static int max32xxx_erase(struct flash_bank *bank, int first, int last) erased = 1; /* Address is first word in page */ - target_write_u32(target, info->flc_base + FLSH_ADDR, banknr * info->sector_size); + target_write_u32(target, info->flc_base + FLC_ADDR, banknr * info->sector_size); /* Write page erase code */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn |= FLSH_CN_ERASE_CODE_PGE; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_ERASE_CODE_PGE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Issue page erase command */ - flsh_cn |= 0x4; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + flash_cn |= FLC_CN_PGE; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Wait until erase complete */ retry = 1000; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash page erase @ 0x%08x", @@ -299,10 +330,10 @@ static int max32xxx_erase(struct flash_bank *bank, int first, int last) } /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Error erasing flash page %i", banknr); - target_write_u32(target, info->flc_base + FLSH_INT, 0); + target_write_u32(target, info->flc_base + FLC_INT, 0); max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; } @@ -347,15 +378,15 @@ static int max32xxx_protect(struct flash_bank *bank, int set, int first, int las for (page = first; page <= last; page++) { if (set) { /* Set the write/erase bit for this page */ - target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg); + target_read_u32(target, info->flc_base + FLC_PROT + (page/32), &temp_reg); temp_reg |= (0x1 << page%32); - target_write_u32(target, info->flc_base + FLSH_PROT + (page/32), temp_reg); + target_write_u32(target, info->flc_base + FLC_PROT + (page/32), temp_reg); bank->sectors[page].is_protected = 1; } else { /* Clear the write/erase bit for this page */ - target_read_u32(target, info->flc_base + FLSH_PROT + (page/32), &temp_reg); + target_read_u32(target, info->flc_base + FLC_PROT + (page/32), &temp_reg); temp_reg &= ~(0x1 << page%32); - target_write_u32(target, info->flc_base + FLSH_PROT + (page/32), temp_reg); + target_write_u32(target, info->flc_base + FLC_PROT + (page/32), temp_reg); bank->sectors[page].is_protected = 0; } } @@ -372,7 +403,7 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, struct working_area *source; struct working_area *write_algorithm; uint32_t address = bank->base + offset; - struct reg_param reg_params[5]; + struct reg_param reg_params[6]; struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; /* power of two, and multiple of word size */ @@ -418,14 +449,23 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, init_reg_param(®_params[2], "r2", 32, PARAM_OUT); init_reg_param(®_params[3], "r3", 32, PARAM_OUT); init_reg_param(®_params[4], "r4", 32, PARAM_OUT); + init_reg_param(®_params[5], "r5", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, source->address); buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size); buf_set_u32(reg_params[2].value, 0, 32, address); - buf_set_u32(reg_params[3].value, 0, 32, wcount); buf_set_u32(reg_params[4].value, 0, 32, info->flc_base); + + if (info->burst_size_bits == 32) { + buf_set_u32(reg_params[3].value, 0, 32, wcount); + buf_set_u32(reg_params[5].value, 0, 32, WRITE32BIT); + } else { + buf_set_u32(reg_params[3].value, 0, 32, wcount/4); + buf_set_u32(reg_params[5].value, 0, 32, WRITE128BIT); + } + retval = target_run_flash_async_algorithm(target, buffer, wcount, 4, 0, NULL, - 5, reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info); + 6, reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info); if (retval == ERROR_FLASH_OPERATION_FAILED) LOG_ERROR("error %d executing max32xxx flash write algorithm", retval); @@ -437,6 +477,7 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer, destroy_reg_param(®_params[2]); destroy_reg_param(®_params[3]); destroy_reg_param(®_params[4]); + destroy_reg_param(®_params[5]); return retval; } @@ -445,7 +486,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, { struct max32xxx_flash_bank *info = bank->driver_priv; struct target *target = bank->target; - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; uint32_t address = offset; uint32_t remaining = count; uint32_t words_remaining; @@ -463,9 +504,16 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, if (info->probed == 0) return ERROR_FLASH_BANK_NOT_PROBED; - if (offset & 0x3) { - LOG_WARNING("offset size must be word aligned"); - return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + if (info->burst_size_bits == 32) { + if (offset & 0x3) { + LOG_ERROR("offset size must be 32-bit aligned"); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } + } else { + if (offset & 0xF) { + LOG_ERROR("offset size must be 128-bit aligned"); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } } if (offset + count > bank->size) @@ -478,16 +526,13 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, return retval; if (remaining >= 4) { - /* write in 32-bit units */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* try using a block write */ + + /* 128-bit align the words_remaining */ words_remaining = remaining / 4; - retval = max32xxx_write_block(bank, buffer, offset, words_remaining); + words_remaining -= words_remaining % 4; + retval = max32xxx_write_block(bank, buffer, offset, words_remaining); if (retval != ERROR_OK) { if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) LOG_DEBUG("writing flash word-at-a-time"); @@ -496,31 +541,30 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, return ERROR_FLASH_OPERATION_FAILED; } } else { - /* all 32-bit words have been written */ + /* all words_remaining have been written */ buffer += words_remaining * 4; address += words_remaining * 4; remaining -= words_remaining * 4; } } - if ((remaining >= 4) && ((address & 0x1F) != 0)) { - /* write in 32-bit units until we are 128-bit aligned */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + if ((info->burst_size_bits == 32) && (remaining >= 4)) { + /* write in 32-bit units*/ + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_32BIT; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - while ((remaining >= 4) && ((address & 0x1F) != 0)) { - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + while (remaining >= 4) { + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, buffer); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Wait until flash operation is complete */ retry = 10; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address); @@ -534,27 +578,26 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, } if ((info->burst_size_bits == 128) && (remaining >= 16)) { - /* write in 128-bit bursts while we can */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - - flsh_cn &= 0xFFFFFFEF; - flsh_cn |= 0x08000000; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - target_write_u32(target, info->flc_base + FLSH_ADDR, address); + /* write in 128-bit units */ + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn &= ~(FLC_CN_32BIT); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); while (remaining >= 16) { + target_write_u32(target, info->flc_base + FLC_ADDR, address); + if ((address & 0xFFF) == 0) LOG_DEBUG("Writing @ 0x%08x", address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 16, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + target_write_buffer(target, info->flc_base + FLC_DATA0, 16, buffer); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Wait until flash operation is complete */ retry = 10; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address); @@ -567,63 +610,78 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, } } - if (remaining >= 4) { + if ((info->burst_size_bits == 32) && remaining > 0) { + /* write remaining bytes in a 32-bit unit */ + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_32BIT; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - /* write in 32-bit units while we can */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + uint8_t last_word[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + int i = 0; - while (remaining >= 4) { - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, buffer); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); - /* Wait until flash operation is complete */ - retry = 10; + while (remaining > 0) { + last_word[i++] = *buffer; + buffer++; + remaining--; + } - do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, last_word); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); - if (retry <= 0) { - LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address); - return ERROR_FLASH_OPERATION_FAILED; - } + /* Wait until flash operation is complete */ + retry = 10; - buffer += 4; - address += 4; - remaining -= 4; + do { + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); + + if (retry <= 0) { + LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address); + return ERROR_FLASH_OPERATION_FAILED; } } - if (remaining > 0) { - /* write remaining bytes in a 32-bit unit */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn &= 0xF7FFFFFF; - flsh_cn |= 0x00000010; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + if ((info->burst_size_bits == 128) && remaining > 0) { + /* write remaining bytes in a 128-bit unit */ + if (target_read_u32(target, info->flc_base + FLC_CN, &flash_cn) != ERROR_OK) { + max32xxx_flash_op_post(bank); + return ERROR_FAIL; + } + + flash_cn &= ~(FLC_CN_32BIT); + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + + uint8_t last_words[16] = {0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}; - uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff}; int i = 0; while (remaining > 0) { - last_word[i++] = *buffer; + last_words[i++] = *buffer; buffer++; remaining--; } - target_write_u32(target, info->flc_base + FLSH_ADDR, address); - target_write_buffer(target, info->flc_base + FLSH_DATA0, 4, last_word); - flsh_cn |= 0x00000001; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + target_write_u32(target, info->flc_base + FLC_ADDR, address); + target_write_buffer(target, info->flc_base + FLC_DATA0, 4, last_words); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 4, 4, last_words + 4); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 8, 4, last_words + 8); + target_write_buffer(target, info->flc_base + FLC_DATA0 + 12, 4, last_words + 12); + flash_cn |= FLC_CN_WR; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); + /* Wait until flash operation is complete */ retry = 10; - do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + if (target_read_u32(target, info->flc_base + FLC_CN, &flash_cn) != ERROR_OK) { + max32xxx_flash_op_post(bank); + return ERROR_FAIL; + } + } while ((--retry > 0) && (flash_cn & FLC_CN_PEND)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash write @ 0x%08x", address); @@ -632,8 +690,8 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer, } /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Flash Error writing 0x%x bytes at 0x%08x", count, offset); max32xxx_flash_op_post(bank); return ERROR_FLASH_OPERATION_FAILED; @@ -688,7 +746,7 @@ static int max32xxx_probe(struct flash_bank *bank) /* Initialize the protection bits for each flash page */ if (max32xxx_protect_check(bank) == ERROR_FLASH_OPER_UNSUPPORTED) - LOG_WARNING("Flash protection not supported on this device"); + LOG_DEBUG("Flash protection not supported on this device"); info->probed = 1; return ERROR_OK; @@ -698,7 +756,7 @@ static int max32xxx_mass_erase(struct flash_bank *bank) { struct target *target = NULL; struct max32xxx_flash_bank *info = NULL; - uint32_t flsh_cn, flsh_int; + uint32_t flash_cn, flash_int; int retval; int retry; info = bank->driver_priv; @@ -732,19 +790,19 @@ static int max32xxx_mass_erase(struct flash_bank *bank) return retval; /* Write mass erase code */ - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - flsh_cn |= FLSH_CN_ERASE_CODE_ME; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + flash_cn |= FLC_CN_ERASE_CODE_ME; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Issue mass erase command */ - flsh_cn |= 0x2; - target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); + flash_cn |= FLC_CN_ME; + target_write_u32(target, info->flc_base + FLC_CN, flash_cn); /* Wait until erase complete */ retry = 1000; do { - target_read_u32(target, info->flc_base + FLSH_CN, &flsh_cn); - } while ((--retry > 0) && (flsh_cn & FLSH_CN_PEND)); + target_read_u32(target, info->flc_base + FLC_CN, &flash_cn); + } while ((--retry > 0) && max32xxx_flash_busy(flash_cn)); if (retry <= 0) { LOG_ERROR("Timed out waiting for flash mass erase"); @@ -752,10 +810,10 @@ static int max32xxx_mass_erase(struct flash_bank *bank) } /* Check access violations */ - target_read_u32(target, info->flc_base + FLSH_INT, &flsh_int); - if (flsh_int & FLSH_INT_AF) { + target_read_u32(target, info->flc_base + FLC_INT, &flash_int); + if (flash_int & FLC_INT_AF) { LOG_ERROR("Error mass erasing"); - target_write_u32(target, info->flc_base + FLSH_INT, 0); + target_write_u32(target, info->flc_base + FLC_INT, 0); return ERROR_FLASH_OPERATION_FAILED; } @@ -930,10 +988,10 @@ COMMAND_HANDLER(max32xxx_handle_protection_check_command) LOG_WARNING("s:<sector number> a:<address> p:<protection bit>"); for (i = 0; i < bank->num_sectors; i += 4) { LOG_WARNING("s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d | s:%03d a:0x%06x p:%d", - (i+0), (i+0)*info->sector_size, bank->sectors[(i+0)].is_protected, - (i+1), (i+1)*info->sector_size, bank->sectors[(i+1)].is_protected, - (i+2), (i+2)*info->sector_size, bank->sectors[(i+2)].is_protected, - (i+3), (i+3)*info->sector_size, bank->sectors[(i+3)].is_protected); + (i+0), (i+0)*info->sector_size, bank->sectors[(i+0)].is_protected, + (i+1), (i+1)*info->sector_size, bank->sectors[(i+1)].is_protected, + (i+2), (i+2)*info->sector_size, bank->sectors[(i+2)].is_protected, + (i+3), (i+3)*info->sector_size, bank->sectors[(i+3)].is_protected); } return ERROR_OK; @@ -994,4 +1052,5 @@ struct flash_driver max32xxx_flash = { .erase_check = default_flash_blank_check, .protect_check = max32xxx_protect_check, .info = get_info, + .free_driver_priv = default_flash_free_driver_priv, }; diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg index 80cb25a..1ee892d 100644 --- a/tcl/target/max32620.cfg +++ b/tcl/target/max32620.cfg @@ -1,28 +1,19 @@ # Maxim Integrated MAX32620 OpenOCD target configuration file # www.maximintegrated.com -# adapter speed -adapter_khz 4000 - -# reset pin configuration +# Set the reset pin configuration reset_config srst_only +adapter_nsrst_delay 200 -if {[using_jtag]} { - jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version -} else { - swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x200000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 32 -# target configuration -target create max32620.cpu cortex_m -chain-position max32620.cpu -max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 +# Setup the reserved TAP +set RSV_TAP 1 -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max32620 flash base address 0x00000000 -# max32620 flash size 0x200000 (2MB) -# max32620 FLC base address 0x40002000 -# max32620 sector (page) size 0x2000 (8kB) -# max32620 clock speed 96 (MHz) -flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96 +source [find target/max32xxx.cfg] diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg index 7182b23..44e62f7 100644 --- a/tcl/target/max32625.cfg +++ b/tcl/target/max32625.cfg @@ -1,28 +1,19 @@ # Maxim Integrated MAX32625 OpenOCD target configuration file # www.maximintegrated.com -# adapter speed -adapter_khz 4000 - -# reset pin configuration +# Set the reset pin configuration reset_config srst_only +adapter_nsrst_delay 200 -if {[using_jtag]} { - jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version -} else { - swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x80000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 32 -# target configuration -target create max32625.cpu cortex_m -chain-position max32625.cpu -max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 +# Setup the reserved TAP +set RSV_TAP 1 -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max32625 flash base address 0x00000000 -# max32625 flash size 0x80000 (512k) -# max32625 FLC base address 0x40002000 -# max32625 sector (page) size 0x2000 (8kB) -# max32625 clock speed 96 (MHz) -flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96 +source [find target/max32xxx.cfg] diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg index f23b0b6..06565ef 100644 --- a/tcl/target/max3263x.cfg +++ b/tcl/target/max3263x.cfg @@ -1,28 +1,39 @@ # Maxim Integrated MAX3263X OpenOCD target configuration file # www.maximintegrated.com -# adapter speed -adapter_khz 4000 +# Set the reset pin configuration +reset_config none -# reset pin configuration -reset_config srst_only +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x200000 +set FLC_BASE 0x40002000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 32 -if {[using_jtag]} { - jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version - jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version -} else { - swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version -} +# Setup the reserved TAP +set RSV_TAP 1 + +source [find target/max32xxx.cfg] + +# Create custom reset sequence +$_CHIPNAME.cpu configure -event reset-init { + + # Reset the peripherals + mww 0x40000848 0xFFFFFFFF + mww 0x4000084C 0xFFFFFFFF -# target configuration -target create max3263x.cpu cortex_m -chain-position max3263x.cpu -max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000 - -# Config Command: flash bank name driver base size chip_width bus_width target [driver_options] -# flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst> -# max3263x flash base address 0x00000000 -# max3263x flash size 0x200000 (2MB) -# max3263x FLC base address 0x40002000 -# max3263x sector (page) size 0x2000 (8kB) -# max3263x clock speed 96 (MHz) -flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96 + sleep 10 + + mww 0x40000848 0x0 + mww 0x4000084C 0x0 + + # Reset the SP + set SP_ADDR [mrw 0x4] + reg sp $SP_ADDR + + # Reset the PC to the Reset_Handler + set RESET_HANDLER_ADDR [mrw 0x4] + reg pc $RESET_HANDLER_ADDR +} diff --git a/tcl/target/max32650.cfg b/tcl/target/max32650.cfg new file mode 100644 index 0000000..1ae0f69 --- /dev/null +++ b/tcl/target/max32650.cfg @@ -0,0 +1,17 @@ +# Maxim Integrated MAX32650 OpenOCD target configuration file +# www.maximintegrated.com + +# Set the reset pin configuration +reset_config srst_only +adapter_nsrst_delay 200 + +# Set flash parameters +set FLASH_BASE 0x10000000 +set FLASH_SIZE 0x300000 +set FLC_BASE 0x40029000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 32 +# set FLASH_BITS 128 + +source [find target/max32xxx.cfg] diff --git a/tcl/target/max32660.cfg b/tcl/target/max32660.cfg new file mode 100644 index 0000000..723d4d5 --- /dev/null +++ b/tcl/target/max32660.cfg @@ -0,0 +1,17 @@ +# Maxim Integrated MAX32660 OpenOCD target configuration file +# www.maximintegrated.com + +# Set the reset pin configuration +reset_config srst_only +adapter_nsrst_delay 200 + +# Set flash parameters +set FLASH_BASE 0x0 +set FLASH_SIZE 0x40000 +set FLC_BASE 0x40029000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 32 +# set FLASH_BITS 128 + +source [find target/max32xxx.cfg] diff --git a/tcl/target/max32665.cfg b/tcl/target/max32665.cfg new file mode 100644 index 0000000..5d05ee4 --- /dev/null +++ b/tcl/target/max32665.cfg @@ -0,0 +1,16 @@ +# Maxim Integrated MAX32665 OpenOCD target configuration file +# www.maximintegrated.com + +# Set the reset pin configuration +reset_config srst_only +adapter_nsrst_delay 200 + +# Set flash parameters +set FLASH_BASE 0x10000000 +set FLASH_SIZE 0x300000 +set FLC_BASE 0x40029000 +set FLASH_SECTOR 0x2000 +set FLASH_CLK 96 +set FLASH_BITS 128 + +source [find target/max32xxx.cfg] diff --git a/tcl/target/max32xxx.cfg b/tcl/target/max32xxx.cfg new file mode 100644 index 0000000..3fb6e66 --- /dev/null +++ b/tcl/target/max32xxx.cfg @@ -0,0 +1,87 @@ +# Maxim Integrated max32xxx OpenOCD drver configuration file +# www.maximintegrated.com + +source [find mem_helper.tcl] +source [find target/swj-dp.tcl] + +# Set the adapter speed +if { [info exists ADAPTER_KHZ] } { + set _ADAPTER_KHZ $ADAPTER_KHZ +} else { + set _ADAPTER_KHZ 2000 +} +adapter_khz $_ADAPTER_KHZ + +# Target configuration +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME max32xxx +} + +# Add reserved TAP +if { [using_jtag] && [info exists RSV_TAP] } { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version + jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version +} else { + swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version +} + + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap + +# Setup working area +if { [info exists WORK_START] } { + set _WORK_START $WORK_START +} else { + set _WORK_START 0x20005000 +} + +if { [info exists WORK_SIZE] } { + set _WORK_SIZE $WORK_SIZE +} else { + set _WORK_SIZE 0x2000 +} + +$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE + +# Configure flash driver +if { [info exists FLASH_BASE] } { + set _FLASH_BASE $FLASH_BASE +} else { + set _FLASH_BASE 0x10000000 +} + +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + set _FLASH_SIZE 0x10000 +} + +if { [info exists FLC_BASE] } { + set _FLC_BASE $FLC_BASE +} else { + set _FLC_BASE 0x40029000 +} + +if { [info exists FLASH_SECTOR] } { + set _FLASH_SECTOR $FLASH_SECTOR +} else { + set _FLASH_SECTOR 0x2000 +} + +if { [info exists FLASH_CLK] } { + set _FLASH_CLK $FLASH_CLK +} else { + set _FLASH_CLK 96 +} + +if { [info exists FLASH_BITS] } { + set _FLASH_BITS $FLASH_BITS +} else { + set _FLASH_BITS 32 +} + +flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \ +$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_BITS -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
