Dear Matthias, thank you for your detailed description about the registers,pc, etc.! This helps a lot =)! There is a RISCV beneath it. Xense
> Gesendet: Sonntag, 03. Februar 2019 um 09:36 Uhr > Von: "Matthias Welwarsky" <[email protected]> > An: [email protected] > Cc: "Xen Mann" <[email protected]> > Betreff: Re: [OpenOCD-devel] adding new interface(TAP): How does openOCD > retrieve the programm counter > > On Mittwoch, 30. Januar 2019 11:27:41 CET Xen Mann wrote: > > Hey there again! > > adding this new interface I wonder, how actually does openOCD retrieve the > > information where the program counter(pc) is on the target. At least the > > connected client which is stepping through the lines of source code must > > have a opinion where controllers pc is. Is this a client or a server thing? > > > Does openOCD know at which address the next and previous pc is? Is it > > configured in the scripts, is it hard coded in the target structure? > > No. OpenOCD is only interested in the state of the target at the point when > you halt it. It retrieves all, or a subset of the registers from the debugged > core, at minimum the PC, processor status and stack pointer. But it doesn't > do > anything with them aside from storing them in a cache. If gdb is attached it > will eventually request the full register file from OpenOCD which is when the > rest of the registers will be loaded. > > The method of loading the registers and halting, stepping, resuming the core > are depending on the core architecture. It depends on the debug support the > hardware has built in. > > Stepping is kind of a special case, depending on whether the core has > hardware > support for single stepping or nowt If not, it will have to be handled with > breakpoints and will may require emulating branch instructions to find the > places where breakpoints have to be put. Gdb will usually do that on its own, > though. > > Your task basically boils down to the question, which part of debug hardware > you access through the JTAG interface. I'm betting it will not be chip > registers but it will be some kind of debug control hardware, maybe > EmbeddedICE if the target core is an ARM9, for RISC-V it will be something > else. This is what the chip designers will have to tell you. > > BR, > Matthias > > > > > > > > > > > _______________________________________________ > > OpenOCD-devel mailing list > > [email protected] > > https://lists.sourceforge.net/lists/listinfo/openocd-devel > > > > > _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
