This refers to "Open On-Chip Debugger 0.10.0+dev-g27c0fd7a
(2020-01-04-05:57)".
When controlling a RISC-V debug module, using system bus access with
autoincrementing bursts, if sbbusyerror is set, openocd currently clears
the error bit by writing 0x00400000 to the sbcs register. This also clears
all the R/W bits in the word (specifically the autoincrement bit and the
access size), but openocd proceeds as though they remained as they were.
The first section of the attached file shows a fragment from the (very
long) openocd.log. Line 7844 shows the initial setting of sbcs, and an
initial burst follows. Lines 7873/4 show the sbbusyerror bit set, and line
7877 shows the write to clear it. But then the next burst is started
without respecifying autoincrement etc.
openocd should set these bits again, either in the write which clears the
error (perhaps simply by writing back the value just read), or
alternatively by setting the required fields before each burst. The second
section of the attached file gives a patch (untested) provided by a
colleague, taking the second approach.
joe
Debug: 7842 5311 target.c:2166 target_write_buffer(): writing buffer of 44 byte
at 0xc0000000
Debug: 7843 5311 riscv.c:2410 riscv_set_current_hartid(): setting hartid to 0,
was 0
Debug: 7844 5311 riscv-013.c:390 scan(): 40b 0i w 00050000 @38 -> + aaaaaaaa @00
Debug: 7845 5312 riscv-013.c:401 scan(): sbaccess=2 sbautoincrement ->
Debug: 7846 5312 riscv-013.c:390 scan(): 40b 0i - 00000000 @38 -> + aaaaaaaa @00
Debug: 7847 5312 riscv-013.c:390 scan(): 40b 0i w c0000000 @39 -> + aaaaaaaa @00
Debug: 7848 5312 riscv-013.c:390 scan(): 40b 0i - 00000000 @39 -> + aaaaaaaa @00
Debug: 7849 5312 riscv-013.c:2620 write_memory_bus_v1(): transferring burst
starting at address 0x00000000c0000000
Debug: 7850 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000000] writes
0xc00f0137
Debug: 7851 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000004] writes
0x00012023
Debug: 7852 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000008] writes
0xfe012e23
Debug: 7853 5312 riscv-013.c:1942 log_memory_access(): M[0xc000000c] writes
0x00006317
Debug: 7854 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000010] writes
0xccc30313
Debug: 7855 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000014] writes
0x00006397
Debug: 7856 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000018] writes
0xd1838393
Debug: 7857 5312 riscv-013.c:1942 log_memory_access(): M[0xc000001c] writes
0x00032023
Debug: 7858 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000020] writes
0x00430313
Debug: 7859 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000024] writes
0xfe731ce3
Debug: 7860 5312 riscv-013.c:1942 log_memory_access(): M[0xc0000028] writes
0x0680006f
Debug: 7861 5316 batch.c:153 dump_field(): 40b 0i w c00f0137 @3c -> + aaaaaaaa
@00
Debug: 7862 5316 batch.c:153 dump_field(): 40b 0i w 00012023 @3c -> + aaaaaaaa
@00
Debug: 7863 5316 batch.c:153 dump_field(): 40b 0i w fe012e23 @3c -> + aaaaaaaa
@00
Debug: 7864 5316 batch.c:153 dump_field(): 40b 0i w 00006317 @3c -> + aaaaaaaa
@00
Debug: 7865 5316 batch.c:153 dump_field(): 40b 0i w ccc30313 @3c -> + aaaaaaaa
@00
Debug: 7866 5316 batch.c:153 dump_field(): 40b 0i w 00006397 @3c -> + aaaaaaaa
@00
Debug: 7867 5316 batch.c:153 dump_field(): 40b 0i w d1838393 @3c -> + aaaaaaaa
@00
Debug: 7868 5316 batch.c:153 dump_field(): 40b 0i w 00032023 @3c -> + aaaaaaaa
@00
Debug: 7869 5316 batch.c:153 dump_field(): 40b 0i w 00430313 @3c -> + aaaaaaaa
@00
Debug: 7870 5316 batch.c:153 dump_field(): 40b 0i w fe731ce3 @3c -> + aaaaaaaa
@00
Debug: 7871 5316 batch.c:153 dump_field(): 40b 0i w 0680006f @3c -> + aaaaaaaa
@00
Debug: 7872 5316 batch.c:153 dump_field(): 40b 0i - 00000000 @00 -> + aaaaaaaa
@00
Debug: 7873 5316 riscv-013.c:390 scan(): 40b 0i r 00000000 @38 -> + 20450404 @00
Debug: 7874 5316 riscv-013.c:390 scan(): 40b 0i - 00000000 @38 -> + 20450404 @00
Debug: 7875 5317 riscv-013.c:390 scan(): 40b 0i r 00000000 @39 -> + c0000004 @00
Debug: 7876 5317 riscv-013.c:390 scan(): 40b 0i - 00000000 @39 -> + c0000004 @00
Debug: 7877 5317 riscv-013.c:390 scan(): 40b 0i w 00400000 @38 -> + aaaaaaaa @00
Debug: 7878 5317 riscv-013.c:390 scan(): 40b 0i - 00000000 @38 -> + aaaaaaaa @00
Debug: 7879 5317 riscv-013.c:2620 write_memory_bus_v1(): transferring burst
starting at address 0x00000000c0000004
Debug: 7880 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000004] writes
0x00012023
Debug: 7881 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000008] writes
0xfe012e23
Debug: 7882 5317 riscv-013.c:1942 log_memory_access(): M[0xc000000c] writes
0x00006317
Debug: 7883 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000010] writes
0xccc30313
Debug: 7884 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000014] writes
0x00006397
Debug: 7885 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000018] writes
0xd1838393
Debug: 7886 5317 riscv-013.c:1942 log_memory_access(): M[0xc000001c] writes
0x00032023
Debug: 7887 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000020] writes
0x00430313
Debug: 7888 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000024] writes
0xfe731ce3
Debug: 7889 5317 riscv-013.c:1942 log_memory_access(): M[0xc0000028] writes
0x0680006f
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 2f8da5b36..d22612a4a 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2491,15 +2491,15 @@ static int write_memory_bus_v1(struct target *target,
target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
RISCV013_INFO(info);
- uint32_t sbcs = sb_sbaccess(size);
- sbcs = set_field(sbcs, DMI_SBCS_SBAUTOINCREMENT, 1);
- dmi_write(target, DMI_SBCS, sbcs);
-
target_addr_t next_address = address;
target_addr_t end_address = address + count * size;
sb_write_address(target, next_address);
while (next_address < end_address) {
+ uint32_t sbcs = sb_sbaccess(size);
+ sbcs = set_field(sbcs, DMI_SBCS_SBAUTOINCREMENT, 1);
+ dmi_write(target, DMI_SBCS, sbcs);
+
for (uint32_t i = (next_address - address) / size; i < count;
i++) {
const uint8_t *p = buffer + i * size;
if (size > 12)
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