This is an automated email from Gerrit.
Sebastiaan de Schaetzen (sebastiaan.de.schaet...@gmail.com) just uploaded a new
patch set to Gerrit, which you can find at http://openocd.zylin.com/6429
-- gerrit
commit 2ca493b4532ec15374f84da6b401368a4849f402
Author: Sebastiaan de Schaetzen <sebastiaan.de.schaet...@gmail.com>
Date: Wed Aug 11 15:04:34 2021 +0200
flash/stm32l4x: prevent undefined behaviour warnings caused by signed
integer operations
When running OpenOCD with -fsanitize=undefined, a warning is emitted
for an bit-shifting operation whose result cannot be stored in a
signed integer.
This is because (1 << 31) overflows a signed integer, which is
undefined behaviour. By making each of the bit masks act on an
unsigned number, the warning is avoided.
Whether this warning emitted by UBSan would ever manifest into a real
error is debatable, but fixing this does make UBSan happy.
Change-Id: I0455a26b234cb4f5e239a6ba90023d28380e9464
Signed-off-by: Sebastiaan de Schaetzen <sebastiaan.de.schaet...@gmail.com>
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 41b5ff8..ed9d1f0 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -20,31 +20,31 @@
#define OPENOCD_FLASH_NOR_STM32L4X
/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER1 (1 << 2)
+#define FLASH_PG (1U << 0)
+#define FLASH_PER (1U << 1)
+#define FLASH_MER1 (1U << 2)
#define FLASH_PAGE_SHIFT 3
-#define FLASH_CR_BKER (1 << 11)
-#define FLASH_MER2 (1 << 15)
-#define FLASH_STRT (1 << 16)
-#define FLASH_OPTSTRT (1 << 17)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_OBL_LAUNCH (1 << 27)
-#define FLASH_OPTLOCK (1 << 30)
-#define FLASH_LOCK (1 << 31)
+#define FLASH_CR_BKER (1U << 11)
+#define FLASH_MER2 (1U << 15)
+#define FLASH_STRT (1U << 16)
+#define FLASH_OPTSTRT (1U << 17)
+#define FLASH_EOPIE (1U << 24)
+#define FLASH_ERRIE (1U << 25)
+#define FLASH_OBL_LAUNCH (1U << 27)
+#define FLASH_OPTLOCK (1U << 30)
+#define FLASH_LOCK (1U << 31)
/* FLASH_SR register bits */
#define FLASH_BSY (1 << 16)
/* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR (1 << 7) /* Programming sequence error
*/
-#define FLASH_SIZERR (1 << 6) /* Size error */
-#define FLASH_PGAERR (1 << 5) /* Programming alignment error
*/
-#define FLASH_WRPERR (1 << 4) /* Write protection error */
-#define FLASH_PROGERR (1 << 3) /* Programming error */
-#define FLASH_OPERR (1 << 1) /* Operation error */
-#define FLASH_EOP (1 << 0) /* End of operation */
+#define FLASH_PGSERR (1U << 7) /* Programming sequence error
*/
+#define FLASH_SIZERR (1U << 6) /* Size error */
+#define FLASH_PGAERR (1U << 5) /* Programming alignment
error */
+#define FLASH_WRPERR (1U << 4) /* Write protection error */
+#define FLASH_PROGERR (1U << 3) /* Programming error */
+#define FLASH_OPERR (1U << 1) /* Operation error */
+#define FLASH_EOP (1U << 0) /* End of operation */
#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR |
FLASH_PGAERR | \
FLASH_WRPERR |
FLASH_PROGERR | FLASH_OPERR)
@@ -58,7 +58,7 @@
/* FLASH_OPTR register bits */
#define FLASH_RDP_MASK 0xFF
-#define FLASH_TZEN (1 << 31)
+#define FLASH_TZEN (1U << 31)
/* other registers */
#define DBGMCU_IDCODE_G0 0x40015800
--
