This is an automated email from Gerrit.
"Julien Massot <julien.mas...@iot.bzh>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6843
-- gerrit
commit 957c8b56bf79659d5b270abf3cdafd395eab8227
Author: Julien Massot <julien.mas...@iot.bzh>
Date: Tue Feb 1 13:44:05 2022 +0100
aarch64: Add support for ARMv8-R
ARMv8-R platforms are similar to ARMv8-A regarding
JTAG and most cpu registers. ARMv8-R doesn't has MMU
but has MPU instead.
ARMv8-R platforms can be AArch32 only such as Cortex-R52,
or AArch64 capable like Cortex-R82.
Signed-off-by: Julien Massot <julien.mas...@iot.bzh>
Change-Id: Ib086f71685d1e3704b396d478ae9399dd8a391e1
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index d11fd943b..6380c6fff 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1079,9 +1079,12 @@ static int aarch64_post_debug_entry(struct target
*target)
armv8_identify_cache(armv8);
armv8_read_mpidr(armv8);
}
-
- armv8->armv8_mmu.mmu_enabled =
+ if (armv8->is_armv8r) {
+ armv8->armv8_mmu.mmu_enabled = 0;
+ } else {
+ armv8->armv8_mmu.mmu_enabled =
(aarch64->system_control_reg & 0x1U) ? 1 : 0;
+ }
armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
(aarch64->system_control_reg & 0x4U) ? 1 : 0;
armv8->armv8_mmu.armv8_cache.i_cache_enabled =
@@ -2736,6 +2739,25 @@ static int aarch64_init_arch_info(struct target *target,
return ERROR_OK;
}
+static int armv8r_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct aarch64_private_config *pc = target->private_config;
+ struct aarch64_common *aarch64;
+
+ if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
+ return ERROR_FAIL;
+
+ aarch64 = calloc(1, sizeof(struct aarch64_common));
+ if (!aarch64) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
+
+ aarch64->armv8_common.is_armv8r = true;
+
+ return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
+}
+
static int aarch64_target_create(struct target *target, Jim_Interp *interp)
{
struct aarch64_private_config *pc = target->private_config;
@@ -2750,6 +2772,8 @@ static int aarch64_target_create(struct target *target,
Jim_Interp *interp)
return ERROR_FAIL;
}
+ aarch64->armv8_common.is_armv8r = false;
+
return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
}
@@ -2769,12 +2793,16 @@ static void aarch64_deinit_target(struct target *target)
static int aarch64_mmu(struct target *target, int *enabled)
{
+ struct aarch64_common *aarch64 = target_to_aarch64(target);
+ struct armv8_common *armv8 = &aarch64->armv8_common;
if (target->state != TARGET_HALTED) {
LOG_ERROR("%s: target %s not halted", __func__,
target_name(target));
return ERROR_TARGET_INVALID;
}
-
- *enabled =
target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
+ if (armv8->is_armv8r)
+ *enabled = 0;
+ else
+ *enabled =
target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
return ERROR_OK;
}
@@ -3211,3 +3239,39 @@ struct target_type aarch64_target = {
.mmu = aarch64_mmu,
.virt2phys = aarch64_virt2phys,
};
+
+struct target_type armv8r_target = {
+ .name = "armv8r",
+
+ .poll = aarch64_poll,
+ .arch_state = armv8_arch_state,
+
+ .halt = aarch64_halt,
+ .resume = aarch64_resume,
+ .step = aarch64_step,
+
+ .assert_reset = aarch64_assert_reset,
+ .deassert_reset = aarch64_deassert_reset,
+
+ /* REVISIT allow exporting VFP3 registers ... */
+ .get_gdb_arch = armv8_get_gdb_arch,
+ .get_gdb_reg_list = armv8_get_gdb_reg_list,
+
+ .read_memory = aarch64_read_phys_memory,
+ .write_memory = aarch64_write_phys_memory,
+
+ .add_breakpoint = aarch64_add_breakpoint,
+ .add_context_breakpoint = aarch64_add_context_breakpoint,
+ .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
+ .remove_breakpoint = aarch64_remove_breakpoint,
+ .add_watchpoint = aarch64_add_watchpoint,
+ .remove_watchpoint = aarch64_remove_watchpoint,
+ .hit_watchpoint = aarch64_hit_watchpoint,
+
+ .commands = aarch64_command_handlers,
+ .target_create = armv8r_target_create,
+ .target_jim_configure = aarch64_jim_configure,
+ .init_target = aarch64_init_target,
+ .deinit_target = aarch64_deinit_target,
+ .examine = aarch64_examine,
+};
diff --git a/src/target/armv8.h b/src/target/armv8.h
index c30739c8c..2b10879c2 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -211,6 +211,7 @@ struct armv8_common {
uint8_t pa_size;
uint32_t page_size;
uint64_t ttbr_base;
+ bool is_armv8r;
struct armv8_mmu_common armv8_mmu;
diff --git a/src/target/target.c b/src/target/target.c
index 7cdd8d830..0c3cb722a 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -90,6 +90,7 @@ extern struct target_type cortexm_target;
extern struct target_type cortexa_target;
extern struct target_type aarch64_target;
extern struct target_type cortexr4_target;
+extern struct target_type armv8r_target;
extern struct target_type arm11_target;
extern struct target_type ls1_sap_target;
extern struct target_type mips_m4k_target;
@@ -148,6 +149,7 @@ static struct target_type *target_types[] = {
&esirisc_target,
&arcv2_target,
&aarch64_target,
+ &armv8r_target,
&mips_mips64_target,
NULL,
};
--
