[PATCH]: d4afc1674f src/target/arm_semihosting.c: don't halt for non-semihosting svc intructions

[gerrit]

This is an automated email from Gerrit.

"Christian Groessler <ch...@groessler.org>" just uploaded a new patch set to 
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6955

-- gerrit

commit d4afc1674f74932dbd8c6713dbb0005b7cf24578
Author: Christian Groessler <ch...@groessler.org>
Date:   Wed Apr 27 22:24:21 2022 +0200

    src/target/arm_semihosting.c: don't halt for non-semihosting svc intructions
    
    When semihosting is enabled, (almost) any svc instruction halts the
    program and enters the debugger. With this change, non-semihosting
    svc instructions are automatically resumed and the program can handle
    them.
    
    This is for example needed when running Linux on the board under OpenOCD
    control, since every system call enters the debugger otherwise.
    
    Change-Id: Idcdd9d8bea1b00e71ddf1db1eb7d558ed148cc2a
    Signed-off-by: Christian Groessler <ch...@groessler.org>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 507d1cd2c4..94afd3bc3c 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -251,8 +251,10 @@ int arm_semihosting(struct target *target, int *retval)
                        insn = target_buffer_get_u16(target, insn_buf);
 
                        /* SVC 0xab */
-                       if (insn != 0xDFAB)
-                               return 0;
+                       if (insn != 0xDFAB) {
+                               *retval = target_resume(target, 1, 0, 0, 0);
+                               return 1;
+                       }
                } else if (spsr & (1 << 24)) {
                        /* was in Jazelle mode */
                        return 0;
@@ -267,8 +269,10 @@ int arm_semihosting(struct target *target, int *retval)
                        insn = target_buffer_get_u32(target, insn_buf);
 
                        /* SVC 0x123456 */
-                       if (insn != 0xEF123456)
-                               return 0;
+                       if (insn != 0xEF123456) {
+                               *retval = target_resume(target, 1, 0, 0, 0);
+                               return 1;
+                       }
                }
        } else if (is_armv7m(target_to_armv7m(target))) {
                uint16_t insn;

--