This is an automated email from Gerrit.
"Jacek Wuwer <jacek...@gmail.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/6965
-- gerrit
commit d60cbc7358a51fc43e5baebb62b313d5d591c1a3
Author: Jacek Wuwer <jacek...@gmail.com>
Date: Wed May 4 10:15:57 2022 +0200
drivers/vdebug: add support for DAP level interface
This patch adds support for DAP interface to Cadence vdebug driver.
It implements a news transport layer for dapdirect_swd.
Change-Id: I64b02a9e1ce91e552e07fca692879655496f88b6
Signed-off-by: Jacek Wuwer <jacek...@gmail.com>
diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index a81740cb18..069286c5d8 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
/*----------------------------------------------------------------------------
- * Copyright 2020-2021 Cadence Design Systems, Inc.
+ * Copyright 2020-2022 Cadence Design Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
modification,
* are permitted provided that the following conditions are met:
@@ -68,16 +68,18 @@
#include "jtag/interface.h"
#include "jtag/commands.h"
#include "transport/transport.h"
+#include "target/arm_adi_v5.h"
#include "helper/time_support.h"
#include "helper/replacements.h"
#include "helper/log.h"
+#include "helper/list.h"
-#define VD_VERSION 43
+#define VD_VERSION 44
#define VD_BUFFER_LEN 4024
#define VD_CHEADER_LEN 24
#define VD_SHEADER_LEN 16
-#define VD_MAX_MEMORIES 4
+#define VD_MAX_MEMORIES 20
#define VD_POLL_INTERVAL 500
#define VD_SCALE_PSTOMS 1000000000
@@ -149,12 +151,21 @@ enum {
VD_CMD_SIGSET = 0x0a,
VD_CMD_SIGGET = 0x0b,
VD_CMD_JTAGCLOCK = 0x0f,
+ VD_CMD_REGWRITE = 0x15,
+ VD_CMD_REGREAD = 0x16,
VD_CMD_JTAGSHTAP = 0x1a,
VD_CMD_MEMOPEN = 0x21,
VD_CMD_MEMCLOSE = 0x22,
VD_CMD_MEMWRITE = 0x23,
};
+enum {
+ VD_ASPACE_AP = 0x01,
+ VD_ASPACE_DP = 0x02,
+ VD_ASPACE_ID = 0x03,
+ VD_ASPACE_AB = 0x04,
+};
+
enum {
VD_BATCH_NO = 0,
VD_BATCH_WO = 1,
@@ -198,6 +209,11 @@ struct vd_shm {
uint8_t dummy[96]; /* 1fa0; 48+40B+8B; */
};
+struct vd_rdata {
+ struct list_head lh;
+ uint8_t *rdata;
+};
+
struct vd_client {
uint8_t trans_batch;
bool trans_first;
@@ -222,7 +238,7 @@ struct vd_client {
char server_name[32];
char bfm_path[128];
char mem_path[VD_MAX_MEMORIES][128];
- uint8_t *tdo;
+ struct vd_rdata rdataq;
};
struct vd_jtag_hdr {
@@ -234,6 +250,16 @@ struct vd_jtag_hdr {
uint64_t rlen:16;
};
+struct vd_reg_hdr {
+ uint64_t prot:3;
+ uint64_t nonincr:1;
+ uint64_t haddr:12;
+ uint64_t tlen:11;
+ uint64_t asize:3;
+ uint64_t cmd:2;
+ uint64_t addr:32;
+};
+
static struct vd_shm *pbuf;
static struct vd_client vdc;
@@ -333,6 +359,7 @@ static uint32_t vdebug_wait_server(int hsock, struct vd_shm
*pmem)
{
if (!hsock)
return VD_ERR_SOC_OPEN;
+
int st = vdebug_socket_send(hsock, pmem);
if (st <= 0)
return VD_ERR_SOC_SEND;
@@ -343,7 +370,7 @@ static uint32_t vdebug_wait_server(int hsock, struct vd_shm
*pmem)
int rc = pmem->status;
LOG_DEBUG_IO("wait_server: cmd %02" PRIx8 " done, sent %d, rcvd %d,
status %d",
- pmem->cmd, st, rd, rc);
+ pmem->cmd, st, rd, rc);
return rc;
}
@@ -357,6 +384,7 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm,
unsigned int count)
uint8_t *tdo;
int rc;
struct vd_jtag_hdr *hdr;
+ struct vd_rdata *rd;
req = 0; /* beginning of request */
waddr = 0;
@@ -380,7 +408,15 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm,
unsigned int count)
vdc.trans_last = (req + 1) < count ? 0 : 1;
vdc.trans_first = waddr ? 0 : 1;
if (hdr->cmd == 3) { /* read */
- tdo = vdc.tdo;
+ if (!rwords) {
+ rd = &vdc.rdataq;
+ tdo = rd->rdata;
+ } else {
+ rd = list_first_entry(&vdc.rdataq.lh, struct
vd_rdata, lh);
+ tdo = rd->rdata;
+ list_del(&rd->lh);
+ free(rd);
+ }
for (unsigned int j = 0; j < bytes; j++) {
tdo[j] = (pm->rd8[rwords * 8 + j] >> num_pre) |
(pm->rd8[rwords * 8 + j + 1] << (8 - num_pre));
LOG_DEBUG_IO("%04x D0[%02x]:%02x", pm->wid -
count + req, j, tdo[j]);
@@ -392,7 +428,7 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm,
unsigned int count)
waddr += sizeof(struct vd_jtag_hdr) / 4; /* waddr past header */
tdi = (pm->wd8[waddr * 4] >> num_pre) | (pm->wd8[waddr * 4 + 1]
<< (8 - num_pre));
tms = (pm->wd8[waddr * 4 + 4] >> num_pre) | (pm->wd8[waddr * 4
+ 4 + 1] << (8 - num_pre));
- LOG_DEBUG("%04x L:%02d O:%05x @%03x DI:%02x MS:%02x DO:%02x",
+ LOG_DEBUG_IO("%04x L:%02d O:%05x @%03x DI:%02x MS:%02x DO:%02x",
pm->wid - count + req, num, (vdc.trans_first << 14) |
(vdc.trans_last << 15),
waddr - 2, tdi, tms, (tdo ? tdo[0] : 0xdd));
waddr += hwords * 2; /* start of next request */
@@ -410,6 +446,77 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm,
unsigned int count)
pm->offset = 0;
pm->rwords = 0;
pm->waddr = 0;
+ INIT_LIST_HEAD(&vdc.rdataq.lh); /* just in case, list should be
empty */
+
+ return rc;
+}
+
+int vdebug_run_reg_queue(int hsock, struct vd_shm *pm, unsigned int count)
+{
+ unsigned int num, awidth, wwidth;
+ unsigned int req, waddr, rwords;
+ uint8_t aspace;
+ uint32_t addr;
+ int64_t ts, te;
+ uint32_t *data;
+ int rc;
+ struct vd_reg_hdr *hdr;
+ struct vd_rdata *rd;
+
+ req = 0; /* beginning of request */
+ waddr = 0;
+ rwords = 0;
+ pm->wbytes = pm->wwords * vdc.buf_width;
+ pm->rbytes = pm->rwords * vdc.buf_width;
+ ts = timeval_ms();
+ rc = vdebug_wait_server(hsock, pm);
+ while (!rc && (req < count)) { /* loop over requests to read data
and print out */
+ hdr = (struct vd_reg_hdr *)&pm->wd32[waddr];
+ addr = hdr->addr; /* reconstruct data for a
single request */
+ num = hdr->tlen;
+ aspace = hdr->prot;
+ awidth = (1 << hdr->asize);
+ wwidth = (awidth + vdc.buf_width - 1) / vdc.buf_width;
+ vdc.trans_last = (req + 1) < count ? 0 : 1;
+ vdc.trans_first = waddr ? 0 : 1;
+ if (hdr->cmd == 2) { /* read */
+ if (num) {
+ if (!rwords) {
+ rd = &vdc.rdataq;
+ data = (uint32_t *)rd->rdata;
+ } else {
+ rd = list_first_entry(&vdc.rdataq.lh,
struct vd_rdata, lh);
+ data = (uint32_t *)rd->rdata;
+ list_del(&rd->lh);
+ free(rd);
+ }
+ for (unsigned int j = 0; j < num; j++)
+ memcpy(&data[j * awidth],
&pm->rd8[(rwords + j) * awidth], awidth);
+ }
+ LOG_DEBUG_IO("read %04x AS:%02x RG:%02x O:%05x @%03x
D:%08x", pm->wid - count + req, aspace, addr,
+ (vdc.trans_first << 14) |
(vdc.trans_last << 15), waddr, (num ? pm->rd32[rwords] : 0xdead));
+ rwords += num * wwidth;
+ waddr += sizeof(struct vd_reg_hdr) / 4; /* waddr past
header */
+ } else {
+ LOG_DEBUG_IO("write %04x AS:%02x RG:%02x O:%05x @%03x
D:%08x", pm->wid - count + req, aspace, addr,
+ (vdc.trans_first << 14) |
(vdc.trans_last << 15), waddr, pm->wd32[waddr + num + 1]);
+ waddr += sizeof(struct vd_reg_hdr) / 4 + (num * wwidth
* awidth + 3) / 4;
+ }
+ req += 1;
+ }
+
+ if (rc) {
+ LOG_ERROR("0x%x executing transaction", rc);
+ rc = ERROR_FAIL;
+ }
+
+ te = timeval_ms();
+ vdc.targ_time += (uint32_t)(te - ts);
+ pm->offseth = 0; /* reset buffer write address */
+ pm->offset = 0;
+ pm->rwords = 0;
+ pm->waddr = 0;
+ INIT_LIST_HEAD(&vdc.rdataq.lh); /* just in case, list should be
empty */
return rc;
}
@@ -456,6 +563,7 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const
char *path,
return ERROR_FAIL;
}
+ INIT_LIST_HEAD(&vdc.rdataq.lh);
LOG_DEBUG("%s type %0x, period %dps, buffer %dx%dB signals r%04xw%04x",
path, type, vdc.bfm_period, VD_BUFFER_LEN / vdc.buf_width,
vdc.buf_width, vdc.sig_read, vdc.sig_write);
@@ -546,7 +654,7 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm
*pm, uint8_t num_pre,
int rc = 0;
pm->cmd = VD_CMD_JTAGSHTAP;
- vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO) || tdo;
+ vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO);
if (vdc.trans_first)
waddr = 0; /* reset buffer offset */
else
@@ -615,8 +723,17 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm
*pm, uint8_t num_pre,
}
if (tdo) {
+ struct vd_rdata *rd;
+ if (!pm->rwords) {
+ rd = &vdc.rdataq;
+ } else {
+ rd = calloc(1, sizeof(struct vd_rdata));
+ if (!rd) /* check allocation
for 24B */
+ return ERROR_FAIL;
+ list_add_tail(&rd->lh, &vdc.rdataq.lh);
+ }
+ rd->rdata = tdo;
pm->rwords += words; /* keep track of the words
to read */
- vdc.tdo = tdo;
}
pm->wwords = waddr / 2 + hwords; /* payload size *2 to
include both TDI and TMS data */
pm->waddr++;
@@ -633,6 +750,94 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm
*pm, uint8_t num_pre,
return rc;
}
+static int vdebug_reg_write(int hsock, struct vd_shm *pm, const uint32_t reg,
+ const uint32_t data,
uint8_t aspace, uint8_t f_last)
+{
+ uint32_t waddr;
+ struct vd_reg_hdr *hdr;
+ int rc = ERROR_OK;
+
+ pm->cmd = VD_CMD_REGWRITE;
+ vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO);
+ if (vdc.trans_first)
+ waddr = 0; /* reset buffer offset */
+ else
+ waddr = pm->offseth; /* continue from the previous
transaction */
+
+ if (4 * waddr + 2 * sizeof(struct vd_reg_hdr) + 4 > VD_BUFFER_LEN)
+ vdc.trans_last = 1; /* force flush, no room for next request
*/
+
+ hdr = (struct vd_reg_hdr *)&pm->wd32[waddr]; /* 8 bytes header */
+ hdr->prot = aspace;
+ hdr->nonincr = 0;
+ hdr->haddr = 0;
+ hdr->tlen = 1; /* 1 word */
+ hdr->asize = 2; /* 32 bit */
+ hdr->cmd = 1; /* write */
+ hdr->addr = reg;
+ pm->wd32[waddr + 2] = data;
+ pm->wid++;
+ pm->wwords = waddr + 3;
+ pm->waddr++;
+ if (!vdc.trans_last) /* buffered request */
+ pm->offseth = waddr + 3;
+ else
+ rc = vdebug_run_reg_queue(hsock, pm, pm->waddr);
+ vdc.trans_first = vdc.trans_last; /* flush forces trans_first flag */
+
+ return rc;
+}
+
+static int vdebug_reg_read(int hsock, struct vd_shm *pm, const uint32_t reg,
+ uint32_t *data, uint8_t
aspace, uint8_t f_last)
+{
+ uint32_t waddr;
+ struct vd_reg_hdr *hdr;
+ int rc = ERROR_OK;
+
+ pm->cmd = VD_CMD_REGREAD;
+ vdc.trans_last = f_last || (vdc.trans_batch == VD_BATCH_NO);
+ if (vdc.trans_first)
+ waddr = 0; /* reset buffer offset */
+ else
+ waddr = pm->offseth; /* continue from the previous
transaction */
+
+ if (4 * waddr + 2 * sizeof(struct vd_reg_hdr) + 4 > VD_BUFFER_LEN)
+ vdc.trans_last = 1; /* force flush, no room for next request
*/
+
+ hdr = (struct vd_reg_hdr *)&pm->wd32[waddr]; /* 8 bytes header */
+ hdr->prot = aspace;
+ hdr->nonincr = 0;
+ hdr->haddr = 0;
+ hdr->tlen = data ? 1 : 0; /* 1 word */
+ hdr->asize = 2; /* 32 bit */
+ hdr->cmd = 2; /* read */
+ hdr->addr = reg;
+ pm->wid++;
+ if (hdr->tlen) {
+ struct vd_rdata *rd;
+ if (!pm->rwords) {
+ rd = &vdc.rdataq;
+ } else {
+ rd = calloc(1, sizeof(struct vd_rdata));
+ if (!rd) /* check allocation for 24B
*/
+ return ERROR_FAIL;
+ list_add_tail(&rd->lh, &vdc.rdataq.lh);
+ }
+ rd->rdata = (uint8_t *)data;
+ pm->rwords += 1;
+ }
+ pm->wwords = waddr + 2;
+ pm->waddr++;
+ if (!vdc.trans_last) /* buffered request */
+ pm->offseth = waddr + 2;
+ else
+ rc = vdebug_run_reg_queue(hsock, pm, pm->waddr);
+ vdc.trans_first = vdc.trans_last; /* flush forces trans_first flag */
+
+ return rc;
+}
+
static int vdebug_mem_open(int hsock, struct vd_shm *pm, const char *path,
uint8_t ndx)
{
int rc;
@@ -673,6 +878,7 @@ static void vdebug_mem_close(int hsock, struct vd_shm *pm,
uint8_t ndx)
LOG_DEBUG("%" PRIx8 ": %s", ndx, vdc.mem_path[ndx]);
}
+
static int vdebug_init(void)
{
vdc.hsocket = vdebug_socket_open(vdc.server_name, vdc.server_port);
@@ -692,10 +898,13 @@ static int vdebug_init(void)
}
vdc.trans_first = 1;
vdc.poll_cycles = vdc.poll_max;
- uint32_t sig_mask = VD_SIG_RESET | VD_SIG_TRST | VD_SIG_TCKDIV;
+ uint32_t sig_mask = VD_SIG_RESET;
+ if (transport_is_jtag())
+ sig_mask |= VD_SIG_TRST | VD_SIG_TCKDIV;
+
int rc = vdebug_open(vdc.hsocket, pbuf, vdc.bfm_path, vdc.bfm_type,
vdc.bfm_period, sig_mask);
if (rc != 0) {
- LOG_ERROR("cannot connect to %s, rc 0x%x", vdc.bfm_path, rc);
+ LOG_ERROR("0x%x cannot connect to %s", rc, vdc.bfm_path);
close_socket(vdc.hsocket);
vdc.hsocket = 0;
free(pbuf);
@@ -704,7 +913,7 @@ static int vdebug_init(void)
for (uint8_t i = 0; i < vdc.mem_ndx; i++) {
rc = vdebug_mem_open(vdc.hsocket, pbuf,
vdc.mem_path[i], i);
if (rc != 0)
- LOG_ERROR("cannot connect to %s, rc 0x%x",
vdc.mem_path[i], rc);
+ LOG_ERROR("0x%x cannot connect to %s", rc,
vdc.mem_path[i]);
}
LOG_INFO("vdebug %d connected to %s through %s:%" PRIu16,
@@ -811,8 +1020,8 @@ static int vdebug_jtag_scan(struct scan_command *cmd,
uint8_t f_flush)
uint8_t cur_tms_post = i == cmd->num_fields - 1 ? tms_post : 0;
uint8_t cur_flush = i == cmd->num_fields - 1 ? f_flush : 0;
rc = vdebug_jtag_shift_tap(vdc.hsocket, pbuf, cur_num_pre,
cur_tms_pre,
- cmd->fields[i].num_bits, cmd->fields[i].out_value,
cur_num_post, cur_tms_post,
- cmd->fields[i].in_value, cur_flush);
+
cmd->fields[i].num_bits, cmd->fields[i].out_value, cur_num_post, cur_tms_post,
+
cmd->fields[i].in_value, cur_flush);
if (rc)
break;
}
@@ -913,6 +1122,61 @@ static int vdebug_jtag_execute_queue(void)
return rc;
}
+static int vdebug_dap_connect(struct adiv5_dap *dap)
+{
+ return dap_dp_init(dap);
+}
+
+static int vdebug_dap_send_sequence(struct adiv5_dap *dap, enum
swd_special_seq seq)
+{
+ return ERROR_OK;
+}
+
+static int vdebug_dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
+{
+ return vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >>
2, data, VD_ASPACE_DP, 0);
+}
+
+static int vdebug_dap_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
+{
+ return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >>
2, data, VD_ASPACE_DP, 0);
+}
+
+static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
uint32_t *data)
+{
+ if ((reg & DP_SELECT_APBANK) != ap->dap->select) {
+ vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg &
DP_SELECT_APBANK, VD_ASPACE_DP, 0);
+ ap->dap->select = reg & DP_SELECT_APBANK;
+ }
+
+ vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, NULL,
VD_ASPACE_AP, 0);
+
+ return vdebug_reg_read(vdc.hsocket, pbuf, DP_RDBUFF >> 2, data,
VD_ASPACE_DP, 0);
+}
+
+static int vdebug_dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
uint32_t data)
+{
+ if ((reg & DP_SELECT_APBANK) != ap->dap->select) {
+ vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg &
DP_SELECT_APBANK, VD_ASPACE_DP, 0);
+ ap->dap->select = reg & DP_SELECT_APBANK;
+ }
+
+ return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >>
2, data, VD_ASPACE_AP, 0);
+}
+
+static int vdebug_dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
+{
+ return vdebug_reg_write(vdc.hsocket, pbuf, 0, 0x1, VD_ASPACE_AB, 0);
+}
+
+static int vdebug_dap_run(struct adiv5_dap *dap)
+{
+ if (pbuf->waddr)
+ return vdebug_run_reg_queue(vdc.hsocket, pbuf, pbuf->waddr);
+
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(vdebug_set_server)
{
if ((CMD_ARGC != 1) || !strchr(CMD_ARGV[0], ':'))
@@ -951,7 +1215,10 @@ COMMAND_HANDLER(vdebug_set_bfm)
default:
break;
}
- vdc.bfm_type = VD_BFM_JTAG;
+ if (transport_is_dapdirect_swd())
+ vdc.bfm_type = VD_BFM_SWDP;
+ else
+ vdc.bfm_type = VD_BFM_JTAG;
LOG_DEBUG("bfm_path: %s clk_period %ups", vdc.bfm_path, vdc.bfm_period);
return ERROR_OK;
@@ -1062,9 +1329,24 @@ static struct jtag_interface vdebug_jtag_ops = {
.execute_queue = vdebug_jtag_execute_queue,
};
+static const struct dap_ops vdebug_dap_ops = {
+ .connect = vdebug_dap_connect,
+ .send_sequence = vdebug_dap_send_sequence,
+ .queue_dp_read = vdebug_dap_queue_dp_read,
+ .queue_dp_write = vdebug_dap_queue_dp_write,
+ .queue_ap_read = vdebug_dap_queue_ap_read,
+ .queue_ap_write = vdebug_dap_queue_ap_write,
+ .queue_ap_abort = vdebug_dap_queue_ap_abort,
+ .run = vdebug_dap_run,
+ .sync = NULL, /* optional */
+ .quit = NULL, /* optional */
+};
+
+static const char *const vdebug_transports[] = { "jtag", "dapdirect_swd", NULL
};
+
struct adapter_driver vdebug_adapter_driver = {
.name = "vdebug",
- .transports = jtag_only,
+ .transports = vdebug_transports,
.speed = vdebug_jtag_speed,
.khz = vdebug_jtag_khz,
.speed_div = vdebug_jtag_div,
@@ -1073,4 +1355,5 @@ struct adapter_driver vdebug_adapter_driver = {
.quit = vdebug_quit,
.reset = vdebug_reset,
.jtag_ops = &vdebug_jtag_ops,
+ .dap_swd_ops = &vdebug_dap_ops,
};
diff --git a/tcl/board/vd_a53x2_dap.cfg b/tcl/board/vd_a53x2_dap.cfg
new file mode 100644
index 0000000000..4cf5594d32
--- /dev/null
+++ b/tcl/board/vd_a53x2_dap.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set _CORES 2
+set _CHIPNAME a53
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x1000000
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+
+source [find target/swj-dp.tcl]
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_a53x2_jtag.cfg b/tcl/board/vd_a53x2_jtag.cfg
index 869bc4db01..a5e8d24e55 100644
--- a/tcl/board/vd_a53x2_jtag.cfg
+++ b/tcl/board/vd_a53x2_jtag.cfg
@@ -11,7 +11,7 @@ set _MEMSIZE 0x1000000
set _CPUTAPID 0x5ba00477
# vdebug select transport
-#transport select jtag
+transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
diff --git a/tcl/board/vd_m4_dap.cfg b/tcl/board/vd_m4_dap.cfg
new file mode 100644
index 0000000000..691b6235f6
--- /dev/null
+++ b/tcl/board/vd_m4_dap.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through DAP
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME m4
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x10000
+
+# vdebug select transport
+transport select dapdirect_swd
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
+
+source [find target/swj-dp.tcl]
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_cortex_m.cfg]
diff --git a/tcl/board/vd_m4_jtag.cfg b/tcl/board/vd_m4_jtag.cfg
index ca21476d29..4c795ebfd0 100644
--- a/tcl/board/vd_m4_jtag.cfg
+++ b/tcl/board/vd_m4_jtag.cfg
@@ -10,7 +10,7 @@ set _MEMSIZE 0x10000
set _CPUTAPID 0x4ba00477
# vdebug select transport
-#transport select jtag
+transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
diff --git a/tcl/board/vd_m7_jtag.cfg b/tcl/board/vd_m7_jtag.cfg
new file mode 100644
index 0000000000..880ef9b4c2
--- /dev/null
+++ b/tcl/board/vd_m7_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m7 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME m7
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x100000
+set _CPUTAPID 0x0ba02477
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/tcl/board/vd_pulpissimo_jtag.cfg b/tcl/board/vd_pulpissimo_jtag.cfg
index 69dd9e6dbe..a3f5a84886 100644
--- a/tcl/board/vd_pulpissimo_jtag.cfg
+++ b/tcl/board/vd_pulpissimo_jtag.cfg
@@ -9,7 +9,7 @@ set _HARTID 0x20
set _CPUTAPID 0x249511c3
# vdebug select transport
-#transport select jtag
+transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
diff --git a/tcl/board/vd_swerv_jtag.cfg b/tcl/board/vd_swerv_jtag.cfg
index ff6c6835fc..c5d33f268a 100644
--- a/tcl/board/vd_swerv_jtag.cfg
+++ b/tcl/board/vd_swerv_jtag.cfg
@@ -11,7 +11,7 @@ set _MEMSTART 0x00000000
set _MEMSIZE 0x10000
# vdebug select transport
-#transport select jtag
+transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
diff --git a/tcl/target/vd_riscv.cfg b/tcl/target/vd_riscv.cfg
index b42b25a3a5..f08cb1ac8b 100644
--- a/tcl/target/vd_riscv.cfg
+++ b/tcl/target/vd_riscv.cfg
@@ -14,5 +14,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-coreid $_HARTID
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
+riscv set_mem_access sysbus progbuf
--
