This is an automated email from Gerrit.
"Michele Bisogno <michele.bisogno...@renesas.com>" just uploaded a new patch
set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6974
-- gerrit
commit ccd7f9e91f4841054d810b0a14d62022b41567b8
Author: micbis <michele.bisogno...@renesas.com>
Date: Thu May 12 15:17:49 2022 +0200
tcl/target/renesas_rz_five: Added RZ/Five
Added support for the new Renesas RISC-V
device: RZ/Five
Signed-off-by: micbis <michele.bisogno...@renesas.com>
Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
diff --git a/tcl/target/renesas_rz_five.cfg b/tcl/target/renesas_rz_five.cfg
new file mode 100644
index 0000000000..286bb9f5ce
--- /dev/null
+++ b/tcl/target/renesas_rz_five.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/Five SoC
+#
+# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single)
(1.0 GHz)
+
+transport select jtag
+
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME r9A07g043u
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
--
