[PATCH]: 2319d2e329 cortex_m: fix soft_reset_halt

[gerrit]

This is an automated email from Gerrit.

"Fedi Bouzazi <fedi.bouz...@st.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7514

-- gerrit

commit 2319d2e329dc2e007d8a3e3f0c686dc980feebb9
Author: FBOSTM <fedi.bouz...@st.com>
Date:   Tue Feb 28 17:09:34 2023 +0100

    cortex_m: fix soft_reset_halt
    
    fix the execution of soft reset fails with time out error
    (after 100 ms: S_HALT not raised => Target not halted
     => reset not performed).
    Accordingly to ARM DDI0403E.B, chapter
     “B3.2.6 Application Interrupt and Reset Control Register,
    AIRCR before setting DEMCR.VC_CORERESET to perform local system reset,
    we must halt the core otherwisethe behavior is unpredictable.
    
    Signed-off-by: FBOSTM <fedi.bouz...@st.com>
    Change-Id: Ica6b558bd0da26f9f48bef91457305d28f901976

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 88e9bb299f..80e7a303a1 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1152,6 +1152,28 @@ static int cortex_m_soft_reset_halt(struct target 
*target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* Enter Debug state before setting 1 to AIRCR_VECTRESET */
+       retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+       if (retval != ERROR_OK)
+               return retval;
+
+       /* Ensure core halted */
+       while (timeout < 100) {
+               retval = cortex_m_read_dhcsr_atomic_sticky(target);
+               if (retval == ERROR_OK) {
+                       if (cortex_m->dcb_dhcsr & S_HALT) {
+                               LOG_TARGET_DEBUG(target, "core halted, DHCSR 
0x%08" PRIx32, cortex_m->dcb_dhcsr);
+                               cortex_m_poll(target);
+                               return ERROR_OK;
+                       }
+                       LOG_TARGET_DEBUG(target, "waiting for system 
reset-halt, "
+                               "DHCSR 0x%08" PRIx32 ", %d ms",
+                               cortex_m->dcb_dhcsr, timeout);
+               }
+               timeout++;
+               alive_sleep(1);
+       }
+
        /* Enter debug state on reset; restore DEMCR in endreset_event() */
        retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
                        TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
@@ -1168,6 +1190,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
        /* registers are now invalid */
        register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
+       /* reset timeout to 0 */
+       timeout = 0;
+
        while (timeout < 100) {
                retval = cortex_m_read_dhcsr_atomic_sticky(target);
                if (retval == ERROR_OK) {

--