This is an automated email from Gerrit.
"Chris Pardy <christopher.pa...@nuvation.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7831
-- gerrit
commit ef31fd17f20623cfb2e19cc67b6f582846ed150c
Author: Chris Pardy <christopher.pa...@nuvation.com>
Date: Thu Jul 27 11:28:13 2023 -0400
src/rtos/ThreadX.c: Add support for Cortex-M4F Processors
The Threadx debugging plugin was using rtos_standard_cortex_m3_stacking
for all Cortex M devices, this causes issues when using other devices in
the Cortex M family.
This is fixed by adding a get_stacking_info_cortex_m function which will
choose the appropriate stacking scheme based on the presence of a floating
point unit. This is similar to the solution used in src\rtos\FreeRTOS.c.
Change-Id: Id0315985a959c1b5717d5c39bbebd593a5c5e8d5
Signed-off-by: Chris Pardy <christopher.pa...@nuvation.com>
diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
index 5bdd007d42..2782a3bd5a 100644
--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -13,6 +13,8 @@
#include <jtag/jtag.h>
#include "target/target.h"
#include "target/target_type.h"
+#include "target/armv7m.h"
+#include "target/cortex_m.h"
#include "rtos.h"
#include "helper/log.h"
#include "helper/types.h"
@@ -20,6 +22,7 @@
static const struct rtos_register_stacking *get_stacking_info(const struct
rtos *rtos, int64_t stack_ptr);
static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const
struct rtos *rtos, int64_t stack_ptr);
+static const struct rtos_register_stacking *get_stacking_info_cortex_m(const
struct rtos *rtos, int64_t stack_ptr);
static int is_thread_id_valid(const struct rtos *rtos, int64_t thread_id);
static int is_thread_id_valid_arm926ejs(const struct rtos *rtos, int64_t
thread_id);
@@ -135,9 +138,9 @@ static const struct threadx_params threadx_params_list[] = {
40, /*
thread_name_offset; */
48, /*
thread_state_offset; */
136, /* thread_next_offset */
- &rtos_standard_cortex_m3_stacking, /* stacking_info */
+ NULL, /* stacking_info */
1, /*
stacking_info_nb */
- NULL, /* fn_get_stacking_info
*/
+ get_stacking_info_cortex_m, /* fn_get_stacking_info */
NULL, /*
fn_is_thread_id_valid */
},
{
@@ -226,6 +229,51 @@ static int is_thread_id_valid(const struct rtos *rtos,
int64_t thread_id)
return (thread_id != 0);
}
+static const struct rtos_register_stacking *get_stacking_info_cortex_m(const
struct rtos *rtos, int64_t stack_ptr)
+{
+ int retval;
+
+ /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */
+ int cm4_fpu_enabled = 0;
+ struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
+ if (is_armv7m(armv7m_target)) {
+ if (armv7m_target->fp_feature == FPV4_SP) {
+ /* Found ARM v7m target which includes a FPU */
+ uint32_t cpacr;
+
+ retval = target_read_u32(rtos->target, FPU_CPACR,
&cpacr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read CPACR register to
check FPU state");
+ return NULL;
+ }
+
+ /* Check if CP10 and CP11 are set to full access. */
+ if (cpacr & 0x00F00000) {
+ /* Found target with enabled FPU */
+ cm4_fpu_enabled = 1;
+ }
+ }
+ }
+
+ if (cm4_fpu_enabled == 1) {
+ /* Read the LR to decide between stacking with or without FPU */
+ uint32_t lr_svc = 0;
+ retval = target_read_u32(rtos->target,
+ stack_ptr,
+ &lr_svc);
+ if (retval != ERROR_OK) {
+ LOG_OUTPUT("Error reading stack frame from thread");
+ return NULL;
+ }
+ if ((lr_svc & 0x10) == 0)
+ return &rtos_standard_cortex_m4f_fpu_stacking;
+ else
+ return &rtos_standard_cortex_m4f_stacking;
+ }
+
+ return &rtos_standard_cortex_m3_stacking;
+}
+
static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const
struct rtos *rtos, int64_t stack_ptr)
{
const struct threadx_params *param = (const struct threadx_params *)
rtos->rtos_specific_params;
--
