This is an automated email from Gerrit.
"Nishanth Menon <n...@ti.com>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/7854
-- gerrit
commit f8e9c7fb3d6d6ee1b8a5816e2a395539b8bd0fee
Author: Jason Kacines <j-kaci...@ti.com>
Date: Wed Aug 9 09:10:13 2023 -0500
tcl/target/ti_k3: Add AM62A7 SoC
Add support for the TI K3 family AM62A7 SoC.
For further details, see https://www.ti.com/lit/pdf/spruj16a
Change-Id: Ie69bde4895f34b04f9967f63d1ca9c8149c50b8a
Signed-off-by: Jason Kacines <j-kaci...@ti.com>
Signed-off-by: Nishanth Menon <n...@ti.com>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 20b78ba895..d25b41ed43 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -14,6 +14,8 @@
# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62a7: https://www.ti.com/lit/pdf/spruj16a
+# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
#
source [find target/swj-dp.tcl]
@@ -119,6 +121,31 @@ switch $_soc {
set _gp_mcu_cores 1
set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
}
+ am62a7 {
+ set _CHIPNAME am62a7
+ set _K3_DAP_TAPID 0x0bb8d02f
+
+ # AM62a7 has 1 clusters of 4 A53 cores.
+ set _armv8_cpu_name a53
+ set _armv8_cores 4
+ set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+ set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+ # AM62a7 has 1 cluster of 1 R5s core.
+ set _r5_cores 1
+ set R5_NAMES {main0_r5.0}
+ set R5_DBGBASE {0x9d410000}
+ set R5_CTIBASE {0x9d418000}
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+ }
j721e {
set _CHIPNAME j721e
set _K3_DAP_TAPID 0x0bb6402f
--
