[PATCH]: fff495abeb mips32: read cpu id from the cp0 PRId register

[gerrit]

This is an automated email from Gerrit.

"Paul Fertser <fercer...@gmail.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7858

-- gerrit

commit fff495abeb355711acac13e4bb90d2aa4c32bb4d
Author: Artur Rojek <cont...@artur-rojek.eu>
Date:   Sun Aug 13 16:47:28 2023 +0200

    mips32: read cpu id from the cp0 PRId register
    
    Read the Processor Identification (PRId) CP0 register and store its
    value in the mips_ejtag context.
    
    Change-Id: Iad1ba689cc535720893af8fa76d69c7077698a5b
    Signed-off-by: Artur Rojek <cont...@artur-rojek.eu>
    Signed-off-by: Paul Fertser <fercer...@gmail.com>

diff --git a/src/target/mips32.c b/src/target/mips32.c
index ce16a7b5d6..0c58b565ef 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -693,6 +693,25 @@ int mips32_enable_interrupts(struct target *target, int 
enable)
        return ERROR_OK;
 }
 
+/* read processor identification cp0 register */
+int mips32_read_c0_prid(struct target *target)
+{
+       struct mips32_common *mips32 = target_to_mips32(target);
+       struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+       int retval;
+
+       if (ejtag_info->prid)
+               return ERROR_OK;
+
+       retval = mips32_cp0_read(ejtag_info, &ejtag_info->prid, 15, 0);
+       if (retval != ERROR_OK) {
+               LOG_ERROR("processor id not available, failed to read cp0 PRId 
register");
+               ejtag_info->prid = 0;
+       }
+
+       return retval;
+}
+
 /* read config to config3 cp0 registers and log isa implementation */
 int mips32_read_config_regs(struct target *target)
 {
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 81b6d649d8..8999fafb0f 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -408,6 +408,8 @@ int mips32_enable_interrupts(struct target *target, int 
enable);
 
 int mips32_examine(struct target *target);
 
+int mips32_read_c0_prid(struct target *target);
+
 int mips32_read_config_regs(struct target *target);
 
 int mips32_register_commands(struct command_context *cmd_ctx);
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index eb80742d65..b95838cb4b 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -191,6 +191,7 @@ struct mips_ejtag {
        uint32_t idcode;
        uint32_t ejtag_ctrl;
        int fast_access_save;
+       uint32_t prid;          /* processor identification register */
        uint32_t config_regs;   /* number of config registers read */
        uint32_t config[4];     /* cp0 config to config3 */
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 14e3f3b27a..58f06d0d7e 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -100,6 +100,8 @@ static int mips_m4k_debug_entry(struct target *target)
        /* attempt to find halt reason */
        mips_m4k_examine_debug_reason(target);
 
+       mips32_read_c0_prid(target);
+
        mips32_read_config_regs(target);
 
        /* default to mips32 isa, it will be changed below if required */

--