Rolf, I don't know PCoC6, so I don't know if it accepts "connect under reset". But if the only way to achieve it is through the time critical sequence you have described, then I'm afraid that no user space tool will be able to reliably produce it. It's not a problem due to OpenOCD, but due to Windows/MacOS/Linux/FreeBDS/... or any other operating system that cannot guarantee such timing! And if you add in the middle the USB stack to communicate with the JTAG/SWD, the situation gets even worse and strongly dependent on the adapter and USB1 vs USB3 vs USB3.
Probably Cypress implements this time critical sequence directly in the RTOS inside their own adapter/probe, where they can guarantee the correct timing. Antonio On Thu, Dec 7, 2023 at 11:53 PM Rolf | Onethinx <r...@onethinx.com> wrote: > Hi all, > > I am working on PSoC6, dual core CM0+ / CM4 and I need a reset (toggle > pulse: high > low 10 ms > high > wait 100ms > attach SWD on CM4). So the > CPU won’t attach under reset but will attach after about 10-40ms. I will > need set up the .cfg file to have a SRST because the CPU can be in sleep > and an ‘intrusive’ connect is less important. I can setup another attach > cfg if I want a less intrusive attach. > > I tried several option but I didn’t find it worked consistently with all > adapters. I will do more testing tomorrow and try out all suggestions. > > FYI: I updated/rewrote the complete PSoC6.c file as the one currently in > the repo is one of the first versions made by Cypress at the time and if > has many defects. Will commit the update after testing. > > Regards, > Rolf > > > > Op 7 dec. 2023, om 23:04 heeft Antonio Borneo <borneo.anto...@gmail.com> > het volgende geschreven: > > Rolf, > > you can try with > reset_config srst_only srst_nogate connect_assert_srst > but this is not valid for every SoC, so give it a try. > > You can find more details in OpenOCD documentation, but shortly this > command will instruct OpenOCD to: > 1) start and keep the SoC under reset > 2) while the SoC is under reset, OpenOCD will try to set 'halt in reset > vector' > 3) when gdb attaches, the reset is removed and the CPU should halt at > reset vector. > > The tricky point is 2). Some SoC during reset disables the JTAG port > or disables the debug clock, so operation 2) will fail. > > I just tested it on a STM32F4, running this on command line: > openocd -f board/st_nucleo_f4.cfg -c 'reset_config > connect_assert_srst' -c init -c 'reset halt' > and it halts at reset vector even when FW in flash reconfigures the > JTAG pins of when all the clocks are off due to power saving or idle > > Antonio > > On Thu, Dec 7, 2023 at 4:40 PM Tommy Murphy <tommy_mur...@hotmail.com> > wrote: > > > How can I implement an SRST procedure of let’s say 10mS assert > > > Using the `adapter assert/deassert` and `sleep` commands maybe? > > > https://openocd.org/doc/html/General-Commands.html#:~:text=Command%3A%20adapter%20assert%20%5Bsignal,%5Bsignal%20%5Bassert%7Cdeassert%20signal%5D%5D > > https://openocd.org/doc/html/General-Commands.html#:~:text=Command%3A%20sleep%20msec%20%5Bbusy%5D > > > > >
