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"Liam Fletcher <liam.fletc...@microchip.com>" just uploaded a new patch set to
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-- gerrit
commit 108c7a3bc9b6156e453c0604cc9d87558f73b133
Author: Liam Fletcher <liam.fletc...@microchip.com>
Date: Mon May 26 10:30:07 2025 +0100
target: add microchip riscv config
To support members of the PIC64GX and Polarfire SoC family, as well as
soft MiV processor on FPGA
Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
Signed-off-by: Liam Fletcher <liam.fletc...@microchip.com>
diff --git a/tcl/target/microchip_riscv.cfg b/tcl/target/microchip_riscv.cfg
new file mode 100644
index 0000000000..6f469925e3
--- /dev/null
+++ b/tcl/target/microchip_riscv.cfg
@@ -0,0 +1,288 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#------------------------------------------------------------------------------
+# Microchip RISC-V
+#------------------------------------------------------------------------------
+
+transport select jtag
+
+# PolarFire SoC (MPFS) hart id to name lookup table
+array set mpfs_hart_names {
+ 0 hart0_e51
+ 1 hart1_u54_1
+ 2 hart2_u54_2
+ 3 hart3_u54_3
+ 4 hart4_u54_4
+}
+
+# PIC64GX hart id to name lookup table
+array set pic64gx_hart_names {
+ 0 hart0_e51
+ 1 hart1_u54_1
+ 2 hart2_u54_2
+ 3 hart3_u54_3
+ 4 hart4_u54_4
+}
+
+# MPFS devices table
+set mpfs_cpu_tap_info {
+ MPFS025 0x0f8531cf
+ MPFS095 0x0f8181cf
+ MPFS160 0x0f8191cf
+ MPFS250 0x0f81a1cf
+ MPFS460 0x0f81b1cf
+ RTPFS160 0x0f8991cf
+ RTPFS460 0x0f89b1cf
+}
+
+# PIC64GX table
+set pic64gx_tap_info {
+ PIC64GX1000 0x0f8531cf
+}
+
+# PolarFire table
+set polarfire_tap_info {
+ MPF050 0x0f8101cf
+ MPF100 0x0f8111cf
+ MPF200 0x0f8121cf
+ MPF300 0x0f8131cf
+ MPF500 0x0f8141cf
+ RTPF500-A 0x8f8141cf
+ RTPF500 0x0f8941cf
+ MPFS250 0x0f81a1cf
+}
+
+# RTG4 table
+set rtg4_tap_info {
+ RT4P6000 0x007001cf
+ RT4P12000 0x007011cf
+ RT4P16000 0x007021cf
+}
+
+# MiV Soft Processor table
+set miv_tap_info {
+ MiV1 0x10e31913
+ MiV2 0x1c0011cf
+ MiV3 0x1e50105f
+}
+
+proc expected_ids {tap_list} {
+ set str ""
+ dict for {key value} $tap_list {
+ append str "-expected-id" " " $value " "
+ }
+
+ return $str
+}
+
+# Process COREID variable
+if {![exists COREID]} {
+ set COREID -1
+}
+
+# COREID
+# For Multi-Hart setups, check COREID, default to -1 (single debug connection
+# to all harts) if unspecified or invalid (out of range )
+proc handle_coreid {lower_bound upper_bound coreid} {
+ if {$coreid < $lower_bound || $coreid > $upper_bound} {
+ echo [format "Warn : COREID %s not in range
($lower_bound..$upper_bound), defaulting to -1 \
+ (single connection to all harts)" $coreid]
+ set coreid -1
+ }
+
+ return $coreid
+}
+
+# "Direct" debugging (not via FPGA TAP) to MiV
+proc setup_miv {device tap_info} {
+ set irlen 5
+ set expected_ids [expected_ids $tap_info]
+
+ # RISC-V CPU DTM TAP
+ eval jtag newtap $device cpu -irlen $irlen $expected_ids -ignore-version
+ # Mi-V soft core - implicitly single hart
+ set _TARGETNAME_0 $device.miv
+ target create $_TARGETNAME_0 riscv -chain-position $device.cpu
+
+ $_TARGETNAME_0 configure -event reset-init board_reset_init
+ $_TARGETNAME_0 configure -event reset-init init_regs
+
+ # gdb-detach event handler
+ $_TARGETNAME_0 configure -event gdb-detach {
+ # resume execution on debugger detach
+ resume
+ }
+
+ #
+ # Utility procedures
+ #
+
+ proc board_reset_init {} {
+ # call board level reset-init if defined
+ if {[exists -proc do_board_reset_init]} {
+ do_board_reset_init
+ }
+ }
+
+ proc init_regs {} {
+ reg pc 0
+ }
+
+ #
+ # Reset configuration
+ #
+
+ # Only TRSTn supported
+ reset_config trst_only
+}
+
+# MPFS
+proc setup_mpfs {device coreid tap_info hart_names} {
+ set coreid [handle_coreid -1 4 $coreid ]
+
+ # RISC-V CPU DTM TAP
+ set irlen 8
+ set expected_ids [expected_ids $tap_info]
+ eval jtag newtap $device cpu -irlen $irlen $expected_ids -ignore-version
+
+ # PolarFire SoC (MPFS)
+ if {$coreid == -1} {
+ # Single debug connection to all harts
+ set _TARGETNAME_0 $device.$hart_names(0)
+ set _TARGETNAME_1 $device.$hart_names(1)
+ set _TARGETNAME_2 $device.$hart_names(2)
+ set _TARGETNAME_3 $device.$hart_names(3)
+ set _TARGETNAME_4 $device.$hart_names(4)
+
+ target create $_TARGETNAME_0 riscv -chain-position $device.cpu
-coreid 0 -rtos hwthread
+ target create $_TARGETNAME_1 riscv -chain-position $device.cpu
-coreid 1
+ target create $_TARGETNAME_2 riscv -chain-position $device.cpu
-coreid 2
+ target create $_TARGETNAME_3 riscv -chain-position $device.cpu
-coreid 3
+ target create $_TARGETNAME_4 riscv -chain-position $device.cpu
-coreid 4
+ target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2
$_TARGETNAME_3 $_TARGETNAME_4
+
+ $_TARGETNAME_1 configure -event reset-init init_regs
+ $_TARGETNAME_2 configure -event reset-init init_regs
+ $_TARGETNAME_3 configure -event reset-init init_regs
+ $_TARGETNAME_4 configure -event reset-init init_regs
+
+ } else {
+ # Debug connection to a specific hart
+ set _TARGETNAME_0 $device.$hart_names($coreid)
+ target create $_TARGETNAME_0 riscv -chain-position $device.cpu
-coreid $coreid
+ }
+
+ $_TARGETNAME_0 configure -event reset-init board_reset_init
+ $_TARGETNAME_0 configure -event reset-init init_regs
+
+ # gdb-detach event handler
+ $_TARGETNAME_0 configure -event gdb-detach {
+ # resume execution on debugger detach
+ resume
+ }
+
+ #
+ # Utility procedures
+ #
+
+ proc board_reset_init {} {
+ # call board level reset-init if defined
+ if {[exists -proc do_board_reset_init]} {
+ do_board_reset_init
+ }
+ }
+
+ proc init_regs {} {
+ reg pc 0
+ }
+
+ #
+ # Reset configuration
+ #
+
+ # Only TRSTn supported
+ reset_config trst_only
+}
+
+proc setup_pic64gx {device coreid tap_info hart_names } {
+ set coreid [handle_coreid -1 4 $coreid ]
+
+ # RISC-V CPU DTM TAP
+ set irlen 8
+ set expected_ids [expected_ids $tap_info]
+ eval jtag newtap $device cpu -irlen $irlen $expected_ids -ignore-version
+
+ # PIC64GX
+ if {$coreid == -1} {
+ # Single debug connection to all harts
+ set _TARGETNAME_0 $device.$hart_names(0)
+ set _TARGETNAME_1 $device.$hart_names(1)
+ set _TARGETNAME_2 $device.$hart_names(2)
+ set _TARGETNAME_3 $device.$hart_names(3)
+ set _TARGETNAME_4 $device.$hart_names(4)
+
+ target create $_TARGETNAME_0 riscv -chain-position $device.cpu
-coreid 0 -rtos hwthread
+ target create $_TARGETNAME_1 riscv -chain-position $device.cpu
-coreid 1
+ target create $_TARGETNAME_2 riscv -chain-position $device.cpu
-coreid 2
+ target create $_TARGETNAME_3 riscv -chain-position $device.cpu
-coreid 3
+ target create $_TARGETNAME_4 riscv -chain-position $device.cpu
-coreid 4
+ target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2
$_TARGETNAME_3 $_TARGETNAME_4
+
+ $_TARGETNAME_1 configure -event reset-init init_regs
+ $_TARGETNAME_2 configure -event reset-init init_regs
+ $_TARGETNAME_3 configure -event reset-init init_regs
+ $_TARGETNAME_4 configure -event reset-init init_regs
+
+ } else {
+ # Debug connection to a specific hart
+ set _TARGETNAME_0 $device.$hart_names($coreid)
+ target create $_TARGETNAME_0 riscv -chain-position $device.cpu
-coreid $coreid
+ }
+
+ $_TARGETNAME_0 configure -event reset-init board_reset_init
+ $_TARGETNAME_0 configure -event reset-init init_regs
+
+ # gdb-detach event handler
+ $_TARGETNAME_0 configure -event gdb-detach {
+ # resume execution on debugger detach
+ resume
+ }
+
+ #
+ # Utility procedures
+ #
+
+ proc board_reset_init {} {
+ # call board level reset-init if defined
+ if {[exists -proc do_board_reset_init]} {
+ do_board_reset_init
+ }
+ }
+
+ proc init_regs {} {
+ reg pc 0
+ }
+
+ #
+ # Reset configuration
+ #
+
+ # Only TRSTn supported
+ reset_config trst_only
+}
+
+#
+# Handle different riscv based devices
+#
+if {[string range $DEVICE 0 7] eq "pic64gx"} {
+ echo [format "Info : Connecting to member of PIC64GX family"]
+ set ret [setup_pic64gx $DEVICE $COREID $pic64gx_tap_info
$pic64gx_hart_names]
+} elseif {[string range $DEVICE 0 4] eq "mpfs"} {
+ echo [format "Info : Connecting to member of PolarFire SoC family"]
+ set ret [setup_mpfs $DEVICE $COREID $mpfs_cpu_tap_info $mpfs_hart_names]
+} elseif {[string range $DEVICE 0 3] eq "miv"} {
+ echo [format "Info : Connecting to soft MiV processor on FPGA"]
+ set ret [setup_miv $DEVICE $miv_tap_info]
+} else {
+ echo [format "Error: Unknown DEVICE %s" $DEVICE]
+}
--
