[PATCH]: 98d7b4a87b armv8m: Add support for msplim/psplim for targets with no secext

[gerrit]

This is an automated email from Gerrit.

"Ivan <ivan.kryvosh...@infineon.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/8887

-- gerrit

commit 98d7b4a87bcc00fa6e994e9fdc0fb978239e7823
Author: kryvosheiaivan <ivan.kryvosh...@infineon.com>
Date:   Thu Jun 26 19:20:39 2025 +0300

    armv8m: Add support for msplim/psplim for targets with no secext
    
    When armv8m does not have security extension, it still has msplim/psplim 
regs
    implemented, which is described in Cortex-M33 Devices Generic User Guide
    Document ID: 100235_0100_05_en, or at the link:
    
https://developer.arm.com/documentation/100230/0002/functional-description/programmers-model/processor-core-registers-summary
    Tested on cyw20829 along with gdb v14.2.1
    
    Change-Id: I4f060e4df742c6773e79ce0481697361202d544c
    Signed-off-by: kryvosheiaivan <ivan.kryvosh...@infineon.com>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8eaf70f60a..94cd3f683b 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2716,10 +2716,26 @@ int cortex_m_examine(struct target *target)
                if (armv7m->fp_feature != FPV5_MVE_F && armv7m->fp_feature != 
FPV5_MVE_I)
                        armv7m->arm.core_cache->reg_list[ARMV8M_VPR].exist = 
false;
 
-               if (!cortex_m_has_tz(target))
+               bool cm_has_tz = cortex_m_has_tz(target);
+               if (!cm_has_tz)
                        for (size_t idx = ARMV8M_FIRST_REG; idx <= 
ARMV8M_LAST_REG; idx++)
                                armv7m->arm.core_cache->reg_list[idx].exist = 
false;
 
+               /* The MSPLIM_NS and PSPLIM_NS registers are always present on 
ARMv8M, regardless of TZ */
+               if (armv7m->arm.arch == ARM_ARCH_V8M) {
+                       
armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].exist = true;
+                       
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].exist = true;
+
+                       /* If TZ is not implemented, rename xSPLIM_NS to simply 
xSPLIM */
+                       if (!cm_has_tz) {
+                               const char* feature_name = "armv8m.no.secext";
+                               
armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].name = "msplim";
+                               
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].name = "psplim";
+                               
armv7m->arm.core_cache->reg_list[ARMV8M_MSPLIM_NS].feature->name = feature_name;
+                               
armv7m->arm.core_cache->reg_list[ARMV8M_PSPLIM_NS].feature->name = feature_name;
+                       }
+               }
+
                if (!armv7m->is_hla_target) {
                        if (cortex_m->core_info->flags & 
CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K)
                                /* Cortex-M3/M4 have 4096 bytes autoincrement 
range,

--