This is an automated email from Gerrit.
"Henrik Mau <henrik....@analog.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/8979
-- gerrit
commit 9845e4f08f54398e519b2717acd1e507c15a15da
Author: Henrik Mau <henrik....@analog.com>
Date: Mon Jun 30 13:23:23 2025 +0100
tcl/target/max32xxx: Add max3267x support
Add configuration files for max32670, max32672 and max32675
Change-Id: I073db6294740bf46713134d75f718dfc7338156e
Signed-off-by: Henrik Mau <henrik....@analog.com>
diff --git a/tcl/target/max32670.cfg b/tcl/target/max32670.cfg
new file mode 100644
index 0000000000..1042bb6b99
--- /dev/null
+++ b/tcl/target/max32670.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+global rom_bp_enabled
+set rom_bp_enabled "no"
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+ global sp_reset_mode
+ set sp_reset_mode $mode
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+ global sp_reset_mode
+ global _CHIPNAME
+
+ if { ([string compare $sp_reset_mode "init"] == 0) } {
+ set state "reset"
+ while { [string compare $state "reset"] == 0 } {
+ set state [$_CHIPNAME.cpu curstate]
+ $_CHIPNAME.cpu arp_poll
+ }
+ $_CHIPNAME.cpu arp_halt
+ }
+}
+
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+ global sp_reset_mode
+ global rom_bp_enabled
+
+ if { (([string compare $sp_reset_mode "halt"] == 0) || ([string compare
$sp_reset_mode "init"] == 0)) } {
+ halt
+ if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+ rbp 0x00002174
+ }
+ bp 0x00002174 2 hw
+ set rom_bp_enabled "yes"
+ }
+}
+
+$_CHIPNAME.cpu configure -event halted {
+ global sp_reset_mode
+ global rom_bp_enabled
+
+ if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+ rbp 0x00002174
+ set rom_bp_enabled "no"
+ }
+ set sp_reset_mode none
+}
diff --git a/tcl/target/max32672.cfg b/tcl/target/max32672.cfg
new file mode 100644
index 0000000000..26c7c82dbc
--- /dev/null
+++ b/tcl/target/max32672.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Add additional flash bank
+set FLASH_BASE 0x10080000
+set FLC_BASE 0x40029400
+
+flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0
$_CHIPNAME.cpu \
+$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
diff --git a/tcl/target/max32675.cfg b/tcl/target/max32675.cfg
new file mode 100644
index 0000000000..1042bb6b99
--- /dev/null
+++ b/tcl/target/max32675.cfg
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+global rom_bp_enabled
+set rom_bp_enabled "no"
+
+# Override default init_reset{mode} to catch parameter "mode"
+proc init_reset {mode} {
+ global sp_reset_mode
+ set sp_reset_mode $mode
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+ global sp_reset_mode
+ global _CHIPNAME
+
+ if { ([string compare $sp_reset_mode "init"] == 0) } {
+ set state "reset"
+ while { [string compare $state "reset"] == 0 } {
+ set state [$_CHIPNAME.cpu curstate]
+ $_CHIPNAME.cpu arp_poll
+ }
+ $_CHIPNAME.cpu arp_halt
+ }
+}
+
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+ global sp_reset_mode
+ global rom_bp_enabled
+
+ if { (([string compare $sp_reset_mode "halt"] == 0) || ([string compare
$sp_reset_mode "init"] == 0)) } {
+ halt
+ if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+ rbp 0x00002174
+ }
+ bp 0x00002174 2 hw
+ set rom_bp_enabled "yes"
+ }
+}
+
+$_CHIPNAME.cpu configure -event halted {
+ global sp_reset_mode
+ global rom_bp_enabled
+
+ if { ([string compare $rom_bp_enabled "yes"] == 0) } {
+ rbp 0x00002174
+ set rom_bp_enabled "no"
+ }
+ set sp_reset_mode none
+}
--
