This is an automated email from Gerrit.
"zapb <d...@zapb.de>" just uploaded a new patch set to Gerrit, which you can
find at https://review.openocd.org/c/openocd/+/8989
-- gerrit
commit becb3dbcaa0ab528593866fa5014e1bcd1acb40c
Author: Marc Schink <d...@zapb.de>
Date: Wed Jul 9 11:37:30 2025 +0000
target: Use 'bool' data type in mmu()
The variable is already used in some parts of the code as boolean value
but have the wrong data type.
Change-Id: I50ccbf84c6f33a3034de989789c6b17312458ea8
Signed-off-by: Marc Schink <d...@zapb.de>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index f6fc6db4e6..51ef1a82ac 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -50,7 +50,7 @@ static int aarch64_set_hybrid_breakpoint(struct target
*target,
struct breakpoint *breakpoint);
static int aarch64_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int aarch64_mmu(struct target *target, int *enabled);
+static int aarch64_mmu(struct target *target, bool *enabled);
static int aarch64_virt2phys(struct target *target,
target_addr_t virt, target_addr_t *phys);
static int aarch64_read_cpu_memory(struct target *target,
@@ -2528,7 +2528,7 @@ static int aarch64_read_phys_memory(struct target *target,
static int aarch64_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- int mmu_enabled = 0;
+ bool mmu_enabled = false;
int retval;
/* determine if MMU was enabled on target stop */
@@ -2565,7 +2565,7 @@ static int aarch64_write_phys_memory(struct target
*target,
static int aarch64_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
- int mmu_enabled = 0;
+ bool mmu_enabled = false;
int retval;
/* determine if MMU was enabled on target stop */
@@ -2876,7 +2876,7 @@ static void aarch64_deinit_target(struct target *target)
free(aarch64);
}
-static int aarch64_mmu(struct target *target, int *enabled)
+static int aarch64_mmu(struct target *target, bool *enabled)
{
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
@@ -2885,7 +2885,7 @@ static int aarch64_mmu(struct target *target, int
*enabled)
return ERROR_TARGET_NOT_HALTED;
}
if (armv8->is_armv8r)
- *enabled = 0;
+ *enabled = false;
else
*enabled =
target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
return ERROR_OK;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index c9ee62d3d1..c708c1daad 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -238,7 +238,7 @@ static int arm720t_arch_state(struct target *target)
return ERROR_OK;
}
-static int arm720_mmu(struct target *target, int *enabled)
+static int arm720_mmu(struct target *target, bool *enabled)
{
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 9faae9a474..4f19affac5 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -529,7 +529,7 @@ int arm920t_arch_state(struct target *target)
return ERROR_OK;
}
-static int arm920_mmu(struct target *target, int *enabled)
+static int arm920_mmu(struct target *target, bool *enabled)
{
if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 922b02013f..8c31765e1b 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -749,7 +749,7 @@ static int arm926ejs_virt2phys(struct target *target,
target_addr_t virtual, tar
return ERROR_OK;
}
-static int arm926ejs_mmu(struct target *target, int *enabled)
+static int arm926ejs_mmu(struct target *target, bool *enabled)
{
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 3d979bbabd..b2cb75b98f 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -68,7 +68,7 @@ static int cortex_a_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
uint32_t value, uint32_t *dscr);
-static int cortex_a_mmu(struct target *target, int *enabled);
+static int cortex_a_mmu(struct target *target, bool *enabled);
static int cortex_a_mmu_modify(struct target *target, int enable);
static int cortex_a_virt2phys(struct target *target,
target_addr_t virt, target_addr_t *phys);
@@ -113,7 +113,7 @@ static int cortex_a_prep_memaccess(struct target *target,
int phys_access)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
- int mmu_enabled = 0;
+ bool mmu_enabled = false;
if (phys_access == 0) {
arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
@@ -153,7 +153,7 @@ static int cortex_a_post_memaccess(struct target *target,
int phys_access)
}
arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
} else {
- int mmu_enabled = 0;
+ bool mmu_enabled = false;
cortex_a_mmu(target, &mmu_enabled);
if (mmu_enabled)
cortex_a_mmu_modify(target, 1);
@@ -3249,7 +3249,7 @@ static void cortex_a_deinit_target(struct target *target)
free(cortex_a);
}
-static int cortex_a_mmu(struct target *target, int *enabled)
+static int cortex_a_mmu(struct target *target, bool *enabled)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -3259,7 +3259,7 @@ static int cortex_a_mmu(struct target *target, int
*enabled)
}
if (armv7a->is_armv7r)
- *enabled = 0;
+ *enabled = false;
else
*enabled =
target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
@@ -3270,7 +3270,7 @@ static int cortex_a_virt2phys(struct target *target,
target_addr_t virt, target_addr_t *phys)
{
int retval;
- int mmu_enabled = 0;
+ bool mmu_enabled = false;
/*
* If the MMU was not enabled at debug entry, there is no
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 11ef8f9b92..4ba0122ab0 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1520,10 +1520,10 @@ static int riscv_target_resume(struct target *target,
bool current,
debug_execution, false);
}
-static int riscv_mmu(struct target *target, int *enabled)
+static int riscv_mmu(struct target *target, bool *enabled)
{
if (!riscv_enable_virt2phys) {
- *enabled = 0;
+ *enabled = false;
return ERROR_OK;
}
@@ -1542,7 +1542,7 @@ static int riscv_mmu(struct target *target, int *enabled)
if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP)
: priv) == PRV_M) {
LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%"
PRIx64 ").", mstatus);
- *enabled = 0;
+ *enabled = false;
return ERROR_OK;
}
@@ -1550,16 +1550,16 @@ static int riscv_mmu(struct target *target, int
*enabled)
if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
LOG_DEBUG("Couldn't read SATP.");
/* If we can't read SATP, then there must not be an MMU. */
- *enabled = 0;
+ *enabled = false;
return ERROR_OK;
}
if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) ==
SATP_MODE_OFF) {
LOG_DEBUG("MMU is disabled.");
- *enabled = 0;
+ *enabled = false;
} else {
LOG_DEBUG("MMU is enabled.");
- *enabled = 1;
+ *enabled = true;
}
return ERROR_OK;
@@ -1674,7 +1674,7 @@ static int riscv_address_translate(struct target *target,
static int riscv_virt2phys(struct target *target, target_addr_t virtual,
target_addr_t *physical)
{
- int enabled;
+ bool enabled;
if (riscv_mmu(target, &enabled) == ERROR_OK) {
if (!enabled)
return ERROR_FAIL;
diff --git a/src/target/target.c b/src/target/target.c
index 995adbc9d3..1428fac913 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -650,9 +650,9 @@ static int identity_virt2phys(struct target *target,
return ERROR_OK;
}
-static int no_mmu(struct target *target, int *enabled)
+static int no_mmu(struct target *target, bool *enabled)
{
- *enabled = 0;
+ *enabled = false;
return ERROR_OK;
}
@@ -1978,7 +1978,7 @@ int target_alloc_working_area_try(struct target *target,
uint32_t size, struct w
/* Reevaluate working area address based on MMU state*/
if (!target->working_areas) {
int retval;
- int enabled;
+ bool enabled;
retval = target->type->mmu(target, &enabled);
if (retval != ERROR_OK)
diff --git a/src/target/target_type.h b/src/target/target_type.h
index a146fab763..ccbe03a476 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -264,7 +264,7 @@ struct target_type {
int (*write_phys_memory)(struct target *target, target_addr_t
phys_address,
uint32_t size, uint32_t count, const uint8_t *buffer);
- int (*mmu)(struct target *target, int *enabled);
+ int (*mmu)(struct target *target, bool *enabled);
/* after reset is complete, the target can check if things are properly
set up.
*
diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index 8cca9a5e91..f6dc71bacd 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -96,7 +96,7 @@ int x86_32_common_init_arch_info(struct target *t, struct
x86_32_common *x86_32)
return ERROR_OK;
}
-int x86_32_common_mmu(struct target *t, int *enabled)
+int x86_32_common_mmu(struct target *t, bool *enabled)
{
*enabled = true;
return ERROR_OK;
diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index e232747697..7e8672ea00 100644
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -299,7 +299,7 @@ int x86_32_get_gdb_reg_list(struct target *t,
enum target_register_class reg_class);
int x86_32_common_init_arch_info(struct target *target,
struct x86_32_common *x86_32);
-int x86_32_common_mmu(struct target *t, int *enabled);
+int x86_32_common_mmu(struct target *t, bool *enabled);
int x86_32_common_virt2phys(struct target *t, target_addr_t address,
target_addr_t *physical);
int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
uint32_t size, uint32_t count, uint8_t *buffer);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index b3d43ec7e9..7eaef6b8c8 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3126,7 +3126,7 @@ static int xscale_virt2phys(struct target *target,
return ERROR_OK;
}
-static int xscale_mmu(struct target *target, int *enabled)
+static int xscale_mmu(struct target *target, bool *enabled)
{
struct xscale_common *xscale = target_to_xscale(target);
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 3366623d64..1a402743fa 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -1556,7 +1556,7 @@ int xtensa_get_gdb_reg_list(struct target *target,
return ERROR_OK;
}
-int xtensa_mmu_is_enabled(struct target *target, int *enabled)
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled)
{
struct xtensa *xtensa = target_to_xtensa(target);
*enabled = xtensa->core_config->mmu.itlb_entries_count > 0 ||
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index a920f77cdf..daa88b10d1 100644
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -392,7 +392,7 @@ int xtensa_step(struct target *target, bool current,
target_addr_t address,
bool handle_breakpoints);
int xtensa_do_step(struct target *target, bool current, target_addr_t address,
bool handle_breakpoints);
-int xtensa_mmu_is_enabled(struct target *target, int *enabled);
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled);
int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t
size, uint32_t count, uint8_t *buffer);
int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t
count, uint8_t *buffer);
int xtensa_write_memory(struct target *target,
--
