This is an automated email from Gerrit. "zapb <d...@zapb.de>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8991
-- gerrit commit 4cbd8ca856eb3e745cf64d9a8a956328db364b8c Author: Marc Schink <d...@zapb.de> Date: Wed Jul 9 11:45:23 2025 +0000 target/cortex_a: Use 'bool' data type in cortex_a_mmu_modify() The variables are already used as boolean value but have the wrong data type. Change-Id: Ia1660751063993fcf46c86246e93a75089629ab5 Signed-off-by: Marc Schink <d...@zapb.de> diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 42d01c3ac1..d694ec0f28 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -69,7 +69,7 @@ static int cortex_a_unset_breakpoint(struct target *target, static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, uint32_t value, uint32_t *dscr); static int cortex_a_mmu(struct target *target, bool *enabled); -static int cortex_a_mmu_modify(struct target *target, int enable); +static int cortex_a_mmu_modify(struct target *target, bool enable); static int cortex_a_virt2phys(struct target *target, target_addr_t virt, target_addr_t *phys); static int cortex_a_read_cpu_memory(struct target *target, @@ -119,7 +119,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access) arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); cortex_a_mmu(target, &mmu_enabled); if (mmu_enabled) - cortex_a_mmu_modify(target, 1); + cortex_a_mmu_modify(target, true); if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) { /* overwrite DACR to all-manager */ armv7a->arm.mcr(target, 15, @@ -129,7 +129,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access) } else { cortex_a_mmu(target, &mmu_enabled); if (mmu_enabled) - cortex_a_mmu_modify(target, 0); + cortex_a_mmu_modify(target, false); } return ERROR_OK; } @@ -156,7 +156,7 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access) bool mmu_enabled = false; cortex_a_mmu(target, &mmu_enabled); if (mmu_enabled) - cortex_a_mmu_modify(target, 1); + cortex_a_mmu_modify(target, true); } return ERROR_OK; } @@ -165,12 +165,12 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access) /* modify cp15_control_reg in order to enable or disable mmu for : * - virt2phys address conversion * - read or write memory in phys or virt address */ -static int cortex_a_mmu_modify(struct target *target, int enable) +static int cortex_a_mmu_modify(struct target *target, bool enable) { struct cortex_a_common *cortex_a = target_to_cortex_a(target); struct armv7a_common *armv7a = target_to_armv7a(target); int retval = ERROR_OK; - int need_write = 0; + bool need_write = false; if (enable) { /* if mmu enabled at target stop and mmu not enable */ @@ -180,12 +180,12 @@ static int cortex_a_mmu_modify(struct target *target, int enable) } if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) { cortex_a->cp15_control_reg_curr |= 0x1U; - need_write = 1; + need_write = true; } } else { if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) { cortex_a->cp15_control_reg_curr &= ~0x1U; - need_write = 1; + need_write = true; } } @@ -3285,7 +3285,7 @@ static int cortex_a_virt2phys(struct target *target, } /* mmu must be enable in order to get a correct translation */ - retval = cortex_a_mmu_modify(target, 1); + retval = cortex_a_mmu_modify(target, true); if (retval != ERROR_OK) return retval; return armv7a_mmu_translate_va_pa(target, (uint32_t)virt, --