This is an automated email from Gerrit. "Andreas Dannenberg <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9013
-- gerrit commit 4e106cb3ab1d9a1f50a2ada695d978194122985c Author: Andreas Dannenberg <[email protected]> Date: Wed Aug 13 21:22:11 2025 +0900 tcl/target: add Rockchip RK3588 target Change-Id: Ia5da403054b6c9aa41184a4e092a74aa882a267d Signed-off-by: Andreas Dannenberg <[email protected]> diff --git a/tcl/target/rk3588.cfg b/tcl/target/rk3588.cfg new file mode 100644 index 0000000000..7b470268a1 --- /dev/null +++ b/tcl/target/rk3588.cfg @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Rockchip RK3588 Target +# https://www.rock-chips.com/a/en/products/RK35_Series/2022/0926/1660.html +# Andreas Dannenberg <[email protected]> + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rk3588 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x2ba01477 +} + +adapter speed 4000 + +transport select swd + +# Declare the one SWD tap to access the DAP +swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID + +# Create the DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Create target to allow accessing system memory directly +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# Declare the 8 main application cores (4 little cores + 4 big cores) + +# Little cluster (cores 0..3) +set _TARGETNAME $_CHIPNAME.lcore +set $_TARGETNAME.base(0) 0x81004000 +set $_TARGETNAME.base(1) 0x81005000 +set $_TARGETNAME.base(2) 0x81006000 +set $_TARGETNAME.base(3) 0x81007000 +set $_TARGETNAME.cti(0) 0x81014000 +set $_TARGETNAME.cti(1) 0x81015000 +set $_TARGETNAME.cti(2) 0x81016000 +set $_TARGETNAME.cti(3) 0x81017000 + +# Big cluster (cores 4..7) +set _TARGETNAME $_CHIPNAME.bcore +set $_TARGETNAME.base(4) 0x81024000 +set $_TARGETNAME.base(5) 0x81025000 +set $_TARGETNAME.base(6) 0x81026000 +set $_TARGETNAME.base(7) 0x81027000 +set $_TARGETNAME.cti(4) 0x81034000 +set $_TARGETNAME.cti(5) 0x81035000 +set $_TARGETNAME.cti(6) 0x81036000 +set $_TARGETNAME.cti(7) 0x81037000 + +# Build string used to enable SMP mode +set _smp_command "target smp" + +set _cores 8 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + if {$_core < 4} { + set _TARGETNAME $_CHIPNAME.lcore + } else { + set _TARGETNAME $_CHIPNAME.bcore + } + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \ + -dbgbase [set $_TARGETNAME.base($_core)] + + if { $_core != 0 } { + # non-boot core examination may fail + ${_TARGETNAME}$_core configure -defer-examine + } else { + # uncomment to use hardware threads pseudo rtos + # ${_TARGETNAME}$_core configure -rtos hwthread + } + + set _smp_command "$_smp_command ${_TARGETNAME}$_core" +} + +eval $_smp_command + +# Set default target to boot core +targets $_CHIPNAME.lcore0 --
