Hi Tomas, Thanks for your reply! I mean that one can access the standard RISCV debug module/debug module interface through JTAG, however the standard DTM JTAG registers are not available (i.e. the Debug Module Interface Access and DTM Control and Status registers). There is a non-standard JTAG IR which can be used to access the DM/DMI.
Thanks again, Brandon On Wed, Nov 26, 2025 at 9:17 AM Tomas Vanek <[email protected]> wrote: > Brandon, > > could you tell us more what you mean by "The target's JTAG interface does > expose a mechanism for creating memory accesses"? > > BTW See also recent discussion > https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/CAAj6DX2tjx5893gJYK_LhWFAOt_J6XTG32DRkie4Wvw14h-_3A%40mail.gmail.com/#msg59241351 > about DM access over ADI MEM-AP > > Tomas > > > On 25/11/2025 17:56, Brandon Altieri wrote: > > Hello, > > I have a custom RISCV target that I need to enable OpenOCD (and more > specifically, gdb) support for. The target does not implement/use the > standard RISCV Debug Transport Module. > > Wondering if I can get some guidance on where to start here - I'm not so > sure if I'm able to simply override a couple functions (e.g. > dmi_write/dmi_read, dtmcs_scan, etc.) to enable this? The target's JTAG > interface does expose a mechanism for creating memory accesses where the > DM is reachable. > > Thanks in Advance, > > Brandon Altieri > > >
