This is an automated email from Gerrit. "Evgeniy Naydanov <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9488
-- gerrit commit 949da8d9582b79ae33250957db958b3b3943ade0 Author: Evgeniy Naydanov <[email protected]> Date: Wed Feb 25 20:02:35 2026 +0300 target/riscv: drop `riscv_count_harts()` The goal is to simplify the code. Change-Id: I338d8a42d96cd022960fb229fee13869aa06da0a Signed-off-by: Evgeniy Naydanov <[email protected]> diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index bb450ce623..b2b2a2bef4 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1771,8 +1771,7 @@ static int examine(struct target *target) /* Some regression suites rely on seeing 'Examined RISC-V core' to know * when they can connect with gdb/telnet. * We will need to update those suites if we want to change that text. */ - LOG_INFO("Examined RISC-V core; found %d harts", - riscv_count_harts(target)); + LOG_INFO("Examined RISC-V core; found %d harts", dm->hart_count); LOG_INFO(" hart %d: XLEN=%d, misa=0x%" PRIx64, r->current_hartid, r->xlen, r->misa); return ERROR_OK; @@ -1825,13 +1824,6 @@ static int riscv013_authdata_write(struct target *target, uint32_t value, unsign return ERROR_OK; } -static int riscv013_hart_count(struct target *target) -{ - dm013_info_t *dm = get_dm(target); - assert(dm); - return dm->hart_count; -} - /* Try to find out the widest memory access size depending on the selected memory access methods. */ static unsigned int riscv013_data_bits(struct target *target) { @@ -2302,7 +2294,6 @@ static int init_target(struct command_context *cmd_ctx, generic_info->dmi_read = &dmi_read; generic_info->dmi_write = &dmi_write; generic_info->read_memory = read_memory; - generic_info->hart_count = &riscv013_hart_count; generic_info->data_bits = &riscv013_data_bits; generic_info->print_info = &riscv013_print_info; if (!generic_info->version_specific) { @@ -2402,7 +2393,10 @@ static int deassert_reset(struct target *target) int dmi_busy_delay = info->dmi_busy_delay; time_t start = time(NULL); - for (int i = 0; i < riscv_count_harts(target); ++i) { + dm013_info_t *dm = get_dm(target); + if (!dm) + return ERROR_FAIL; + for (int i = 0; i < dm->hart_count; ++i) { int index = i; if (target->rtos) { if (index != target->coreid) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 4ba0122ab0..8adab6a266 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3240,16 +3240,6 @@ int riscv_current_hartid(const struct target *target) return r->current_hartid; } -int riscv_count_harts(struct target *target) -{ - if (!target) - return 1; - RISCV_INFO(r); - if (!r || !r->hart_count) - return 1; - return r->hart_count(target); -} - /** * If write is true: * return true iff we are guaranteed that the register will contain exactly diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index f06b5f516d..7970814ccf 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -182,8 +182,6 @@ struct riscv_info { int (*read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment); - /* How many harts are attached to the DM that this target is attached to? */ - int (*hart_count)(struct target *target); unsigned int (*data_bits)(struct target *target); COMMAND_HELPER((*print_info), struct target *target); @@ -319,10 +317,6 @@ int riscv_current_hartid(const struct target *target); /*** Support functions for the RISC-V 'RTOS', which provides multihart support * without requiring multiple targets. */ -/* Lists the number of harts in the system, which are assumed to be - * consecutive and start with mhartid=0. */ -int riscv_count_harts(struct target *target); - /** Set register, updating the cache. */ int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v); /** Get register, from the cache if it's in there. */ --
