This is an automated email from Gerrit. "Name of user not set <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9520
-- gerrit commit 8834ec7efc6db081908e4e2e25b77c83a1905d15 Author: Frederic Boyer <[email protected]> Date: Thu Apr 9 15:10:22 2026 +0200 tcl/board: add Microchip SAMA7D65 Curiosity board configuration Add board configuration for the SAMA7D65 Curiosity board. Link: https://www.microchip.com/en-us/development-tool/EV63J76A Change-Id: I5f232a31d0155254fa3589f3bb9f84ff6aa6ba8d Signed-off-by: Frederic Boyer <[email protected]> diff --git a/tcl/board/microchip/sama7d65_curiosity.cfg b/tcl/board/microchip/sama7d65_curiosity.cfg new file mode 100644 index 0000000000..ca25bf7f94 --- /dev/null +++ b/tcl/board/microchip/sama7d65_curiosity.cfg @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Board configuration for Microchip SAMA7D65 Curiosity Board +# https://www.microchip.com/en-us/development-tool/EV63J76A +# Datasheet: DS60001851 +# User Guide: DS50003806 +# +# Debug Interface Selection: +# An external JTAG/SWD probe must be connected to J38. +# + +# +# IMPORTANT: +# First-time JTAG Connection on blank board (no AT91Bootstrap in NVM): +# 1. Power on the board via J3 (USB Type-C) or J1 (DC jack) +# 2. ROM code searches for valid boot media +# 3. No valid code found -> ROM enters SAM-BA Monitor +# 4. SAM-BA Monitor enables JTAG -- OpenOCD can now connect +# To force SAM-BA entry on a board with programmed NVM: +# - Remove JP9 (J36) to disable NAND Flash boot [2] +# - Remove JP10 (J39) to disable QSPI Flash boot [2] +# - Remove any SD card from J10 +# +# Typical Boot sequence (when debugging via JTAG/SWD): +# 1. Load AT91Bootstrap to SRAM (0x00100000) +# - Initializes clocks, DDR, peripherals, disables watchdog +# 2. Load application to DDR (0x60000000) +# - Zephyr, Linux, or bare-metal application +# - DDR must be initialized by AT91Bootstrap first +# +# Reset sources on this board: +# - Power-on reset from MCP16502 PMIC +# - User push button SW4 (Board Reset, connected to NRST) +# - External JTAG probe reset via J38 pin 15 (NRST) +# +# Usage with JTAG (default): +# openocd -f interface/jlink.cfg -f board/microchip/sama7d65_curiosity.cfg +# +# Usage with SWD: +# openocd -f interface/jlink.cfg -c "transport select swd" \ +# -f board/microchip/sama7d65_curiosity.cfg + +# Default to JTAG -- silently ignored if already selected +catch { transport select jtag } + +# Target configuration (supports both JTAG and SWD) +source [find target/microchip/sama7d6.cfg] + +# Board-specific adapter speed +# Start at lower speed for reliable initial connection. +# Speed increases to 4 MHz after reset-init event (configured in target file). +adapter speed 1000 + +# Reset configuration for external probe on J38. +# Both SRST (pin 15/NRST) and TRST (pin 3/NTRST) are available +# on the 20-pin JTAG header. +# NTRST (PC22) has an internal pull-up -- safe to connect. +# +# srst_nogate: SRST is not gated by the JTAG state machine -- +# required because NRST resets the entire chip including debug logic. +# +# For probes with only SRST wired (no TRST), use instead: +# reset_config srst_only srst_nogate +# +reset_config trst_and_srst srst_nogate --
