This is an automated email from Gerrit. "Samuel Obuch <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9606
-- gerrit commit 0f1b5378cbf9935eb9441a0285dbf8dcedc72d05 Author: Samuel Obuch <[email protected]> Date: Thu Apr 30 11:27:16 2026 +0200 target/xtensa: fix powered-off counter logic - Counter come_online_probes_num was only set in target init. This can cause issues if the counter is gradually decremented while debugging, for example after each reset. - Recently added active_polled target flag [1] changed the original logic if debug module is not powered. Unsetting active_polled flag, as well as target_examined flag, reverts to the original behavior. [1] - https://review.openocd.org/c/openocd/+/9180 Change-Id: I2f06bc215d46dee6c69925bd683cef85182756c9 Signed-off-by: Samuel Obuch <[email protected]> diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index d1a08c3bd3..751f0c03ba 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -2354,6 +2354,9 @@ int xtensa_poll(struct target *target) "DSR has changed: was 0x%08" PRIx32 " now 0x%08" PRIx32, prev_dsr, xtensa->dbg_mod.core_status.dsr); + if (xtensa_dm_is_powered(&xtensa->dbg_mod)) + /* Reset the powered-off counter */ + xtensa->come_online_probes_num = 3; if (xtensa->dbg_mod.power_status.stath & PWRSTAT_COREWASRESET(xtensa)) { /* if RESET state is persitent */ target->state = TARGET_RESET; @@ -2362,10 +2365,12 @@ int xtensa_poll(struct target *target) xtensa->dbg_mod.core_status.dsr, xtensa->dbg_mod.core_status.dsr & OCDDSR_STOPPED); target->state = TARGET_UNKNOWN; - if (xtensa->come_online_probes_num == 0) + if (xtensa->come_online_probes_num == 0) { target->examined = false; - else + target->active_polled = false; + } else { xtensa->come_online_probes_num--; + } } else if (xtensa_is_stopped(target)) { if (target->state != TARGET_HALTED) { enum target_state oldstate = target->state; --
