On Fri, Jul 17, 2026 at 8:04 AM Jan Matyáš <[email protected]> wrote: > > (Addition to what I posted, to avoid unclarity) > > Jan: (...) All other processing should go to the underlying > transport-specific layers. > > > In other words, I meant that the RISC-V code should be clearly separated into: > > A generic, transport-independent part. > Transport-specific parts (JTAG DTM, ARM ADI, ...). > > The API between those two should be DMI reads & writes (including the > possibility to create batches), as ImproperCatGirl suggests.
What about the code for Sifive BSCAN tunnel JTAG access? Should it be moved in a separate file or at least better confined / separated / modularized? From what I understand BSCAN tunnel is a virtual JTAG behind the real JTAG port of the FPGA. In such a case it looks like the ARM "JTAG Access Port" that can be placed after the DAP (either JTAG or SWD DAP). My idea is that we should first extend OpenOCD to handle multiple adapters simultaneously, then the "virtual" JTAGs like ARM JTAG-AP and Sifive BSCAN would get a clean implementation as additional adapters that are accessed through the main adapter. Today the code for BSCAN tunnel is mixed with the code of DTM and core. If possible, I would like to have both DTM and BSCAN become independent code. Antonio
