On Friday 12 February 2010 11:58:02 Øyvind Harboe wrote: > On Fri, Feb 12, 2010 at 9:29 AM, Marc Pignat <marc.pig...@hevs.ch> wrote: > > On Friday 12 February 2010 08:59:08 David Brownell wrote: > >> On Thursday 11 February 2010, Marc Pignat wrote: > >> > What happens when we flush an address that is not in the data cache? > >> > >> We obviously *want* it to be a NOP... which is what section 2.3.11 of > >> the ARM920T spec (mine says ARM DDI 0151B) seems to imply. Table 2-15: > >> > >> Clean and Invalidate D entry using either index or MVA > >> > >> ... Writes the specified cache line to main memory, if the line is > >> marked valid and dirty. The line is marked not valid. > >> > >> The code uses an MVA (yes?) so if there's no valid/matching cacheline, > >> that would be a NOP. > > > > > > We use MCR p15,0,Rd,c7,c14,2 (Clean and Invalidate DCache entry (using > > Index)) > > but I think we should use MCR p15,0,Rd,c7,c14,1 - Clean and Invalidate > > DCache entry (using MVA) > > Sounds reasonable! > > > > >> > >> > >> However, the ARM920T code is a bit vague about the particular > >> coprocessor ops it's using. I'm not sure I'd trust those 32-bit > >> numbers to match the MCR instructions in the first comment ... and > >> the second has no comment. It'd be worth making them both of those > >> use the MCR() opcode macros. > >> > > > > I will have a look at this! > > Could you try to make the patch I sent work using the correct cache flushing > method? > > I can't make it work, but if I read well int arm920t_write_cp15_interpreted, we should put the address in value...
I mean we use MCR p15,0,r0,... and we put the VMA in r1, so it will be unused? _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
