Hi all!
Here is a fix for my problem, at least.
Problem : Clean and Invalidate DCache is not available in cp15 interpreted mode.
workaround : Use the Invalidate only.
The problem still remains for write back data cache, but at least it will work
for write through.
Marc
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 0973621..340d646 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -536,14 +536,17 @@ int arm920t_write_memory(struct target *target, uint32_t
address,
* by MMU */
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
- LOG_DEBUG("D-Cache enabled, flush and invalidate cache
line");
+ LOG_DEBUG("D-Cache enabled, invalidate cache line");
/* flush and invalidate data cache
*
- * MCR p15,0,Rd,c7,c14,2 - flush and invalidate cache
line using virtual address
+ * MCR p15,0,Rd,c7,c6,1 - Invalidate DCache single
entry using MVA
*
+ * FIXME : Clean and Invalidate instruction is not
+ * available in intepreted mode, so cache in write back
+ * mode will most likely become inconsistent.
*/
- retval = arm920t_write_cp15_interpreted(target,
0xee070f5e, 0x0, address&~0x3);
+ retval = arm920t_write_cp15_interpreted(target,
0xee070f36, 0x0, address&~0x3);
if (retval != ERROR_OK)
return retval;
}
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