Hello Antonio, Tuesday, November 16, 2010, 3:53:53 PM, you wrote: AB> Are you aware of any target, other than SPEAr, that provides memory AB> mapping feature of SPI flash? I quickly searched, but failed.
NXP's LPC1800 (and, I think, LPC4000) have support for that. 7.10.3 SPI Flash Interface (SPIFI) The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.10.3.1 Features • Interfaces to serial flash memory in the main memory map. • Supports classic and 4-bit bidirectional serial protocols. • Half-duplex protocol compatible with various vendors and devices. • Data rates of up to 320 Mbit/s or 10 Mwords/s. • Supports DMA access. -- WBR, Igor mailto:skochin...@mail.ru _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
