On Thu, Dec 30, 2010 at 3:42 PM, Peter Stuge <pe...@stuge.se> wrote: > Jon Masters wrote: >> Oh, on a randomly off-topic engineering note, I'd love to know why the >> Flyswatter contains component Q1 (the NPN transistor) so that to do a >> system reset you don't just pull nSRST low but actually set A_nSRST high >> and have that go into Q1, which results in pulling system reset low >> indirectly. Is this because we might end up sinking a lot of current? >> Does anyone with an EE/circuit design background happen to know? > > It's not so much about current as it is about voltage. The chip > driving the transistor only has to provide a high enough voltage to > saturate the NPN. This is fairly easy with any digital chip. In > return, the transistor effectively acts as an open collector output, > which will accept a wide range of voltage levels, according to the > transistor data, and can still pull the signal to GND when the > transistor is saturated. > > With a good choice of transistor the driving chip can be 3V3 and the > driven /SRST signal can be much much lower. I think this is what > Flyswatter does.
Sorry Jon, I skipped your message since not involved in the subject. I partially agree with Peter. The transistor can be used as a valid voltage level shifter. I've just checked the schematic of Flyswatter adapter. The nSRST part is common with many JTAG adapters. The main reason for using the transistor in these circuits is to build a "wired AND". Wikipedia does not have a valid description for "wired AND" circuit, but a reasonable one is available in http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/00-intro/03-stdlogic/wired-and.html On the target board, nSRST can have many sources, e.g.: - reset button - watchdog circuit - power-good detector - JTAG All such sources have to be combined together in a single nSRST signal. The role is: nSRST is high when all the reset sources are high too, equivalent to the behaviour of the "AND" gate http://en.wikipedia.org/wiki/AND_gate In this case, "wired AND" is a good replacement for the AND gate. All the reset sources must have "open collector" output ("open drain" in case of CMOS devices). It means their output can only be either at low level or left floating. On the target board there must be one passive pull-up, a resistor to Vcc, that provides the high level when all the sources are floating. Best Regards, Antonio Borneo _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
