2011/7/5 Igor Skochinsky <skochin...@mail.ru>: > Hello Drasko, > > Tuesday, July 5, 2011, 7:01:44 PM, you wrote: > > DD> On Tue, Jul 5, 2011 at 6:17 PM, Spencer Oliver <s...@spen-soft.co.uk> > wrote: >>> I think your patch is ok, but would be better if it checks the arch version >>> and issue a warning about cache writes not supported or something along >>> those lines. > > DD> On the first look, this can be accomplished by reading CP0 PRId > DD> register, but Revision field is not quite well explained. > > DD> I have no idea how to obtain info if the proc is MIPS32/64 Rev2 compliant. > > You should use the Config register (CP0 Register 16). AT field (bits > 14:13) tells if it's MIPS32 or MIPS64, and AR (12:10) is the release.
Hi Igor, thanks, I just took a quick look, and I thought that CP0 PRId would be more appropriate. I saw that bits 7:0 encode the release, but I did not get the codes - they are not well explained in the doc. Maybe CP0 Config would be a better place to look, though naming is not suggestive - Config is used to configure your CPU (it should be RW) and ID is where you want to read Read Only information... I will look tomorrow again, I do not have docs at my disposal now. BTW. CP0 Config (reg 16) has 3 selects. Which one did you mention - 0, 1 or 2 ? I think that I will end up writing both "cache" and "synci" version, and switch in dependence of architecture used. I just want to write mips32_cp0_read() and mips_cp0_write() functions before, which I started today, so that we have more versatile interface. I need this in order to read cache line size and similar cache configs if I want to use "cache" instruction (which I so wanted to avoid, but life is though...) BR, Drasko _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
