Hello to everyone,
Please I'm trying to develop a 64b OR1K. I understood that the instructions
are 32-bits, the question I have is: according with the specification it
seems as two instructions per word of 64b, fetched every time, so is the
compiler packing two inst into the same word ? Or it will place as {32'b0,
instr} /{inst,'32b0}, assuming 64b registers ?
I ask because this will affect the way I map my wires into the decoding
phase of the datapath. And teh question before, is also important to help me
understand how to make the arrangements between cPU<->MMU, to decode the
instructions coming from a L1, that has 64b words.
--
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