Thanks Pete,
My problem is to find: assuming 64b regiusters, for a 64b processor, how the
INSTRUCTIONS are placed into a 64b reg ? So I asked before is {32'b0,inst}
or {inst,32'b0} ?Because the compiler has to generate it in some way, as
well the architecture has to interpret the 64b reg in a specific manner, I
understand that the instr only needs 4-bytes, no prob, so which ones the
31:16 or 15:0 ? that is it ., the problem is so far in the architecture
specification I didn't found such information. Thanks for the the Mor1k
suggestion, I will check it in more details once I start to implement the
cache set-associativity.
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